Nanowire NMOS Logic Inverter Characterization

Nanowire NMOS Logic Inverter Characterization

This study is the first to demonstrate characteristics optimization of nanowire N-Channel Metal Oxide Semiconductor (NW-MOS) logic inverter. Noise margins and inflection voltage of transfer characteristics are used as limiting factors in this optimization. A computer-based model used to produce stat...

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Main Author: Naif, Yasir Hashim
Format: Article
Published: American Scientific Publishers 2016
Subjects:
TK Electrical engineering. Electronics Nuclear engineering
Online Access:http://umpir.ump.edu.my/id/eprint/12987/
http://umpir.ump.edu.my/id/eprint/12987/
id ump-12987
recordtype eprints
spelling ump-129872017-08-22T06:52:12Z http://umpir.ump.edu.my/id/eprint/12987/ Nanowire NMOS Logic Inverter Characterization Naif, Yasir Hashim TK Electrical engineering. Electronics Nuclear engineering This study is the first to demonstrate characteristics optimization of nanowire N-Channel Metal Oxide Semiconductor (NW-MOS) logic inverter. Noise margins and inflection voltage of transfer characteristics are used as limiting factors in this optimization. A computer-based model used to produce static characteristics of NW-NMOS logic inverter. In this research two circuit configuration of NW-NMOS inverter was studied, in first NW-NMOS circuit, the noise margin for (low input-high output) condition was very low. For second NMOS circuit gives excellent noise margins, and results indicate that optimization depends on applied voltage to the inverter. Increasing gate to source voltage with (2/1) nanowires ratio results better noise margins. Increasing of applied DC load transistor voltage tends to increasing in decreasing noise margins; decreasing this voltage will improve noise margins significantly. American Scientific Publishers 2016-06 Article PeerReviewed Naif, Yasir Hashim (2016) Nanowire NMOS Logic Inverter Characterization. Journal of Nanoscience and Nanotechnology, 16 (6). pp. 5923-5928. ISSN 1533-4880 (Print); 1533-4899 (Online) http://www.aspbs.com/jnn/
repository_type Digital Repository
institution_category Local University
institution Universiti Malaysia Pahang
building UMP Institutional Repository
collection Online Access
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
Naif, Yasir Hashim
Nanowire NMOS Logic Inverter Characterization
description This study is the first to demonstrate characteristics optimization of nanowire N-Channel Metal Oxide Semiconductor (NW-MOS) logic inverter. Noise margins and inflection voltage of transfer characteristics are used as limiting factors in this optimization. A computer-based model used to produce static characteristics of NW-NMOS logic inverter. In this research two circuit configuration of NW-NMOS inverter was studied, in first NW-NMOS circuit, the noise margin for (low input-high output) condition was very low. For second NMOS circuit gives excellent noise margins, and results indicate that optimization depends on applied voltage to the inverter. Increasing gate to source voltage with (2/1) nanowires ratio results better noise margins. Increasing of applied DC load transistor voltage tends to increasing in decreasing noise margins; decreasing this voltage will improve noise margins significantly.
format Article
author Naif, Yasir Hashim
author_facet Naif, Yasir Hashim
author_sort Naif, Yasir Hashim
title Nanowire NMOS Logic Inverter Characterization
title_short Nanowire NMOS Logic Inverter Characterization
title_full Nanowire NMOS Logic Inverter Characterization
title_fullStr Nanowire NMOS Logic Inverter Characterization
title_full_unstemmed Nanowire NMOS Logic Inverter Characterization
title_sort nanowire nmos logic inverter characterization
publisher American Scientific Publishers
publishDate 2016
url http://umpir.ump.edu.my/id/eprint/12987/
http://umpir.ump.edu.my/id/eprint/12987/
first_indexed 2023-09-18T22:15:06Z
last_indexed 2023-09-18T22:15:06Z
_version_ 1777415284204765184

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