Pencirian proses penyediaan titanium silisida untuk kegunaan saling hubung litar bersepadu CMOS

Characterization of the titanium silicide process preparation for the application of interconnection in CMOS integrated circuit has been characterized. The process characterize are titanium deposition, selective wet etching, native oxide removal and thermal budget adjustment of reflow- anneal bor...

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Main Authors:	Uda Hashim, Burhanuddin Yeop Majlis, Sahbudin Shaari
Format:	Article
Published:	2000
Online Access:	http://journalarticle.ukm.my/1368/ http://journalarticle.ukm.my/1368/

id	ukm-1368
recordtype	eprints
spelling	ukm-13682011-10-11T03:45:21Z http://journalarticle.ukm.my/1368/ Pencirian proses penyediaan titanium silisida untuk kegunaan saling hubung litar bersepadu CMOS Uda Hashim, Burhanuddin Yeop Majlis, Sahbudin Shaari, Characterization of the titanium silicide process preparation for the application of interconnection in CMOS integrated circuit has been characterized. The process characterize are titanium deposition, selective wet etching, native oxide removal and thermal budget adjustment of reflow- anneal borophosphosilicate glass. Titanium film was sputter-deposited at various times by PVD system. The relationship between titanium deposition time and film thickness is plotted. The relation Y = 3.8X0.89 which was generated by the graph is employed to determine deposition time at any specific thickness. The solution which is the mixture of NH4OH, 30% H2O2, H2O (1:1:5) for solution 1, H2SO4 10% HF, H2O (30:1:69) for solution 2, and H2SO4 30% H2O2 (1: 1) for solution 3 have been tested for titanium selectivity wet etching. Base on the calculation, the etching rate of the solution 1, 2, and 3 are 0.15 nm/s, 7.8 nm/s and 1.16 nm/s, respectively. The wafer, which is dipped in the HF solution before titanium deposition revealing a better silicide/silicon, interface after heat treatment process. The reduction thermal budget of BPSG reflow-anneal from 900°C to 850°C for 30 minutes using furnace couple with additional anneal at 950°C for 60 seconds rapid 60 seconds rapid thermal annealer revealed the same surface topography with the wafer that annealed at 900°C for 30 minutes using conventional furnace 2000 Article PeerReviewed Uda Hashim, and Burhanuddin Yeop Majlis, and Sahbudin Shaari, (2000) Pencirian proses penyediaan titanium silisida untuk kegunaan saling hubung litar bersepadu CMOS. Jurnal Kejuruteraan, 12 . http://www.ukm.my/jkukm/index.php/jkukm
repository_type	Digital Repository
institution_category	Local University
institution	Universiti Kebangasaan Malaysia
building	UKM Institutional Repository
collection	Online Access
description	Characterization of the titanium silicide process preparation for the application of interconnection in CMOS integrated circuit has been characterized. The process characterize are titanium deposition, selective wet etching, native oxide removal and thermal budget adjustment of reflow- anneal borophosphosilicate glass. Titanium film was sputter-deposited at various times by PVD system. The relationship between titanium deposition time and film thickness is plotted. The relation Y = 3.8X0.89 which was generated by the graph is employed to determine deposition time at any specific thickness. The solution which is the mixture of NH4OH, 30% H2O2, H2O (1:1:5) for solution 1, H2SO4 10% HF, H2O (30:1:69) for solution 2, and H2SO4 30% H2O2 (1: 1) for solution 3 have been tested for titanium selectivity wet etching. Base on the calculation, the etching rate of the solution 1, 2, and 3 are 0.15 nm/s, 7.8 nm/s and 1.16 nm/s, respectively. The wafer, which is dipped in the HF solution before titanium deposition revealing a better silicide/silicon, interface after heat treatment process. The reduction thermal budget of BPSG reflow-anneal from 900°C to 850°C for 30 minutes using furnace couple with additional anneal at 950°C for 60 seconds rapid 60 seconds rapid thermal annealer revealed the same surface topography with the wafer that annealed at 900°C for 30 minutes using conventional furnace
format	Article
author	Uda Hashim, Burhanuddin Yeop Majlis, Sahbudin Shaari,
spellingShingle	Uda Hashim, Burhanuddin Yeop Majlis, Sahbudin Shaari, Pencirian proses penyediaan titanium silisida untuk kegunaan saling hubung litar bersepadu CMOS
author_facet	Uda Hashim, Burhanuddin Yeop Majlis, Sahbudin Shaari,
author_sort	Uda Hashim,
title	Pencirian proses penyediaan titanium silisida untuk kegunaan saling hubung litar bersepadu CMOS
title_short	Pencirian proses penyediaan titanium silisida untuk kegunaan saling hubung litar bersepadu CMOS
title_full	Pencirian proses penyediaan titanium silisida untuk kegunaan saling hubung litar bersepadu CMOS
title_fullStr	Pencirian proses penyediaan titanium silisida untuk kegunaan saling hubung litar bersepadu CMOS
title_full_unstemmed	Pencirian proses penyediaan titanium silisida untuk kegunaan saling hubung litar bersepadu CMOS
title_sort	pencirian proses penyediaan titanium silisida untuk kegunaan saling hubung litar bersepadu cmos
publishDate	2000
url	http://journalarticle.ukm.my/1368/ http://journalarticle.ukm.my/1368/
first_indexed	2023-09-18T19:33:08Z
last_indexed	2023-09-18T19:33:08Z
_version_	1777405094793314304

Pencirian proses penyediaan titanium silisida untuk kegunaan saling hubung litar bersepadu CMOS

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