Pencirian proses penyediaan titanium silisida untuk kegunaan saling hubung litar bersepadu CMOS
Characterization of the titanium silicide process preparation for the application of interconnection in CMOS integrated circuit has been characterized. The process characterize are titanium deposition, selective wet etching, native oxide removal and thermal budget adjustment of reflow- anneal bor...
| Main Authors: | , , |
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| Format: | Article |
| Published: |
2000
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| Online Access: | http://journalarticle.ukm.my/1368/ http://journalarticle.ukm.my/1368/ |
| Summary: | Characterization of the titanium silicide process preparation for the application of
interconnection in CMOS integrated circuit has been characterized. The process
characterize are titanium deposition, selective wet etching, native oxide removal and
thermal budget adjustment of reflow- anneal borophosphosilicate glass. Titanium film
was sputter-deposited at various times by PVD system. The relationship between
titanium deposition time and film thickness is plotted. The relation Y = 3.8X0.89 which
was generated by the graph is employed to determine deposition time at any specific
thickness. The solution which is the mixture of NH4OH, 30% H2O2, H2O (1:1:5) for
solution 1, H2SO4 10% HF, H2O (30:1:69) for solution 2, and H2SO4 30% H2O2 (1: 1)
for solution 3 have been tested for titanium selectivity wet etching. Base on the
calculation, the etching rate of the solution 1, 2, and 3 are 0.15 nm/s, 7.8 nm/s and
1.16 nm/s, respectively. The wafer, which is dipped in the HF solution before titanium
deposition revealing a better silicide/silicon, interface after heat treatment process.
The reduction thermal budget of BPSG reflow-anneal from 900°C to 850°C for 30
minutes using furnace couple with additional anneal at 950°C for 60 seconds rapid 60
seconds rapid thermal annealer revealed the same surface topography with the wafer
that annealed at 900°C for 30 minutes using conventional furnace |
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