Design of a multi valued current mode comparator
In this paper, a low-power quaternary comparator circuit using current-mode CMOS multiple-valued logic (MVL) circuits has been presented. Existing MVL comparator circuits consume high power. The circuit presented in this paper low power. It has been simulated with PSPICE using the transistor mode...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
INSI Publications
2011
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| Subjects: | |
| Online Access: | http://irep.iium.edu.my/7353/ http://irep.iium.edu.my/7353/ http://irep.iium.edu.my/7353/1/662-666.pdf |
| Summary: | In this paper, a low-power quaternary comparator circuit using current-mode CMOS
multiple-valued logic (MVL) circuits has been presented. Existing MVL comparator circuits consume
high power. The circuit presented in this paper low power. It has been simulated with PSPICE using
the transistor model parameter values of the BSIM3 NMOS model V3.2 for 0.13um CMOS process. With a 1.3-volt power supply, simulations show that the proposed quaternary comparator consumes 0.107 mW total average static power and a sampling rate 500MHz. Power and speed for comparators
designed in these technologies are discussed. The comparator design is suitable for the needs of mixed signal
integrated circuit design and can be implemented as a conversion circuit for systems based on
multiple-valued logic design. |
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