Efficient cache replacement policy for minimising error rate in L2-STT-MRAM caches

The current research statistics for cache designing reveals that Spin Torque Transfer Magnetic RAMs (STT-MRAMs) have become one of the most promising technologies in the field of memory chip design, gaining a lot of attention from researchers due to its dynamic direct map and data access policies...

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Main Authors:	Olanrewaju, Rashidah Funke, Khan, Burhan Ul Islam, Khan, Abdul Raouf, Yaacob, Mashkuri, Alam, Md. Moktarul
Format:	Article
Language:	English English
Published:	Inderscience Publishers 2018
Subjects:	T10.5 Communication of technical information
Online Access:	http://irep.iium.edu.my/70884/ http://irep.iium.edu.my/70884/ http://irep.iium.edu.my/70884/ http://irep.iium.edu.my/70884/7/70884%20Efficient%20cache%20replacement%20policy%20for%20minimising%20error%20rate.pdf http://irep.iium.edu.my/70884/8/70884%20Efficient%20cache%20replacement%20policy%20for%20minimising%20error%20rate%20SCOPUS.pdf

id	iium-70884
recordtype	eprints
spelling	iium-708842019-07-12T07:54:27Z http://irep.iium.edu.my/70884/ Efficient cache replacement policy for minimising error rate in L2-STT-MRAM caches Olanrewaju, Rashidah Funke Khan, Burhan Ul Islam Khan, Abdul Raouf Yaacob, Mashkuri Alam, Md. Moktarul T10.5 Communication of technical information The current research statistics for cache designing reveals that Spin Torque Transfer Magnetic RAMs (STT-MRAMs) have become one of the most promising technologies in the field of memory chip design, gaining a lot of attention from researchers due to its dynamic direct map and data access policies for reducing the average cost i.e. both time and energy optimisation. In this paper, the vulnerability of STT-MRAM caches has been investigated to examine the effect of workloads as well as process variations for characterising the reliability of STT-MRAM cache. The current study is intended to analyse and evaluate an existing efficient cache replacement policy namely Least Error Rate (LER) which utilises Hamming Distance (HD) computations to reduce the Write Error Rate (WER) of L2-STT-MRAM caches with acceptable overheads. The performance analysis of the algorithm ensures its effectiveness in reducing the WER and cost overheads as compared to the conventional LRU techniques. Inderscience Publishers 2018 Article PeerReviewed application/pdf en http://irep.iium.edu.my/70884/7/70884%20Efficient%20cache%20replacement%20policy%20for%20minimising%20error%20rate.pdf application/pdf en http://irep.iium.edu.my/70884/8/70884%20Efficient%20cache%20replacement%20policy%20for%20minimising%20error%20rate%20SCOPUS.pdf Olanrewaju, Rashidah Funke and Khan, Burhan Ul Islam and Khan, Abdul Raouf and Yaacob, Mashkuri and Alam, Md. Moktarul (2018) Efficient cache replacement policy for minimising error rate in L2-STT-MRAM caches. International Journal of Grid and Utility Computing, 9 (4). pp. 307-321. ISSN 1741-847X E-ISSN 1741-8488 https://www.inderscience.com/info/inarticle.php?artid=95434 10.1504/IJGUC.2018.095434
repository_type	Digital Repository
institution_category	Local University
institution	International Islamic University Malaysia
building	IIUM Repository
collection	Online Access
language	English English
topic	T10.5 Communication of technical information
spellingShingle	T10.5 Communication of technical information Olanrewaju, Rashidah Funke Khan, Burhan Ul Islam Khan, Abdul Raouf Yaacob, Mashkuri Alam, Md. Moktarul Efficient cache replacement policy for minimising error rate in L2-STT-MRAM caches
description	The current research statistics for cache designing reveals that Spin Torque Transfer Magnetic RAMs (STT-MRAMs) have become one of the most promising technologies in the field of memory chip design, gaining a lot of attention from researchers due to its dynamic direct map and data access policies for reducing the average cost i.e. both time and energy optimisation. In this paper, the vulnerability of STT-MRAM caches has been investigated to examine the effect of workloads as well as process variations for characterising the reliability of STT-MRAM cache. The current study is intended to analyse and evaluate an existing efficient cache replacement policy namely Least Error Rate (LER) which utilises Hamming Distance (HD) computations to reduce the Write Error Rate (WER) of L2-STT-MRAM caches with acceptable overheads. The performance analysis of the algorithm ensures its effectiveness in reducing the WER and cost overheads as compared to the conventional LRU techniques.
format	Article
author	Olanrewaju, Rashidah Funke Khan, Burhan Ul Islam Khan, Abdul Raouf Yaacob, Mashkuri Alam, Md. Moktarul
author_facet	Olanrewaju, Rashidah Funke Khan, Burhan Ul Islam Khan, Abdul Raouf Yaacob, Mashkuri Alam, Md. Moktarul
author_sort	Olanrewaju, Rashidah Funke
title	Efficient cache replacement policy for minimising error rate in L2-STT-MRAM caches
title_short	Efficient cache replacement policy for minimising error rate in L2-STT-MRAM caches
title_full	Efficient cache replacement policy for minimising error rate in L2-STT-MRAM caches
title_fullStr	Efficient cache replacement policy for minimising error rate in L2-STT-MRAM caches
title_full_unstemmed	Efficient cache replacement policy for minimising error rate in L2-STT-MRAM caches
title_sort	efficient cache replacement policy for minimising error rate in l2-stt-mram caches
publisher	Inderscience Publishers
publishDate	2018
url	http://irep.iium.edu.my/70884/ http://irep.iium.edu.my/70884/ http://irep.iium.edu.my/70884/ http://irep.iium.edu.my/70884/7/70884%20Efficient%20cache%20replacement%20policy%20for%20minimising%20error%20rate.pdf http://irep.iium.edu.my/70884/8/70884%20Efficient%20cache%20replacement%20policy%20for%20minimising%20error%20rate%20SCOPUS.pdf
first_indexed	2023-09-18T21:40:36Z
last_indexed	2023-09-18T21:40:36Z
_version_	1777413114379108352

Efficient cache replacement policy for minimising error rate in L2-STT-MRAM caches

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