Efficient cache replacement policy for minimising error rate in L2-STT-MRAM caches
The current research statistics for cache designing reveals that Spin Torque Transfer Magnetic RAMs (STT-MRAMs) have become one of the most promising technologies in the field of memory chip design, gaining a lot of attention from researchers due to its dynamic direct map and data access policies...
| Main Authors: | , , , , |
|---|---|
| Format: | Article |
| Language: | English English |
| Published: |
Inderscience Publishers
2018
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| Subjects: | |
| Online Access: | http://irep.iium.edu.my/70884/ http://irep.iium.edu.my/70884/ http://irep.iium.edu.my/70884/ http://irep.iium.edu.my/70884/7/70884%20Efficient%20cache%20replacement%20policy%20for%20minimising%20error%20rate.pdf http://irep.iium.edu.my/70884/8/70884%20Efficient%20cache%20replacement%20policy%20for%20minimising%20error%20rate%20SCOPUS.pdf |
Internet
http://irep.iium.edu.my/70884/http://irep.iium.edu.my/70884/
http://irep.iium.edu.my/70884/
http://irep.iium.edu.my/70884/7/70884%20Efficient%20cache%20replacement%20policy%20for%20minimising%20error%20rate.pdf
http://irep.iium.edu.my/70884/8/70884%20Efficient%20cache%20replacement%20policy%20for%20minimising%20error%20rate%20SCOPUS.pdf