The impact of scaling on single event upset in 6T and 12T SRAMs from 130 to 22 nm CMOS technology

As transistor sizes scale down to nanometres dimensions, CMOS circuits become more sensitive to radiation. High-performance static random access memory (SRAM) cells are prone to radiation-induced single event upsets (SEU) which come from the natural space environment. The SEU generates a soft error...

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Main Authors:	Yusop, N. S., Nordin, Anis Nurashikin, Khairi, M. Azim, Hasbullah, Nurul Fadzlin
Format:	Article
Language:	English English
Published:	Taylor & Francis 2018
Subjects:	TK7800 Electronics. Computer engineering. Computer hardware. Photoelectronic devices
Online Access:	http://irep.iium.edu.my/69761/ http://irep.iium.edu.my/69761/ http://irep.iium.edu.my/69761/ http://irep.iium.edu.my/69761/19/69761%20The%20impact%20of%20scaling%20on%20single%20event%20upset%20in%206T%20and%2012T.pdf http://irep.iium.edu.my/69761/2/69761_The%20impact%20of%20scaling%20on%20single%20event%20upset_scopus.pdf

id	iium-69761
recordtype	eprints
spelling	iium-697612019-07-15T01:50:21Z http://irep.iium.edu.my/69761/ The impact of scaling on single event upset in 6T and 12T SRAMs from 130 to 22 nm CMOS technology Yusop, N. S. Nordin, Anis Nurashikin Khairi, M. Azim Hasbullah, Nurul Fadzlin TK7800 Electronics. Computer engineering. Computer hardware. Photoelectronic devices As transistor sizes scale down to nanometres dimensions, CMOS circuits become more sensitive to radiation. High-performance static random access memory (SRAM) cells are prone to radiation-induced single event upsets (SEU) which come from the natural space environment. The SEU generates a soft error in the transistor due to the strike of an ionizing particle. Thus, this paper compares the endurance of 12T SRAM and 6T SRAM circuit on 130 up to 22 nm CMOS technology towards SEU. Besides that, this paper discusses the trend of critical linear energy transfer (LET) and collected charge due to technology scaling for the respective circuit. The critical LET (LETcrit) and critical charge (Qcrit) of 6T are approximately 50% lower compared with 12T SRAMs. Taylor & Francis 2018-12 Article NonPeerReviewed application/pdf en http://irep.iium.edu.my/69761/19/69761%20The%20impact%20of%20scaling%20on%20single%20event%20upset%20in%206T%20and%2012T.pdf application/pdf en http://irep.iium.edu.my/69761/2/69761_The%20impact%20of%20scaling%20on%20single%20event%20upset_scopus.pdf Yusop, N. S. and Nordin, Anis Nurashikin and Khairi, M. Azim and Hasbullah, Nurul Fadzlin (2018) The impact of scaling on single event upset in 6T and 12T SRAMs from 130 to 22 nm CMOS technology. Radiation Effects and Defects in Solids, 173 (11-12). pp. 1090-1104. ISSN 1042-0150 https://www.tandfonline.com/doi/abs/10.1080/10420150.2018.1542695 10.1080/10420150.2018.1542695
repository_type	Digital Repository
institution_category	Local University
institution	International Islamic University Malaysia
building	IIUM Repository
collection	Online Access
language	English English
topic	TK7800 Electronics. Computer engineering. Computer hardware. Photoelectronic devices
spellingShingle	TK7800 Electronics. Computer engineering. Computer hardware. Photoelectronic devices Yusop, N. S. Nordin, Anis Nurashikin Khairi, M. Azim Hasbullah, Nurul Fadzlin The impact of scaling on single event upset in 6T and 12T SRAMs from 130 to 22 nm CMOS technology
description	As transistor sizes scale down to nanometres dimensions, CMOS circuits become more sensitive to radiation. High-performance static random access memory (SRAM) cells are prone to radiation-induced single event upsets (SEU) which come from the natural space environment. The SEU generates a soft error in the transistor due to the strike of an ionizing particle. Thus, this paper compares the endurance of 12T SRAM and 6T SRAM circuit on 130 up to 22 nm CMOS technology towards SEU. Besides that, this paper discusses the trend of critical linear energy transfer (LET) and collected charge due to technology scaling for the respective circuit. The critical LET (LETcrit) and critical charge (Qcrit) of 6T are approximately 50% lower compared with 12T SRAMs.
format	Article
author	Yusop, N. S. Nordin, Anis Nurashikin Khairi, M. Azim Hasbullah, Nurul Fadzlin
author_facet	Yusop, N. S. Nordin, Anis Nurashikin Khairi, M. Azim Hasbullah, Nurul Fadzlin
author_sort	Yusop, N. S.
title	The impact of scaling on single event upset in 6T and 12T SRAMs from 130 to 22 nm CMOS technology
title_short	The impact of scaling on single event upset in 6T and 12T SRAMs from 130 to 22 nm CMOS technology
title_full	The impact of scaling on single event upset in 6T and 12T SRAMs from 130 to 22 nm CMOS technology
title_fullStr	The impact of scaling on single event upset in 6T and 12T SRAMs from 130 to 22 nm CMOS technology
title_full_unstemmed	The impact of scaling on single event upset in 6T and 12T SRAMs from 130 to 22 nm CMOS technology
title_sort	impact of scaling on single event upset in 6t and 12t srams from 130 to 22 nm cmos technology
publisher	Taylor & Francis
publishDate	2018
url	http://irep.iium.edu.my/69761/ http://irep.iium.edu.my/69761/ http://irep.iium.edu.my/69761/ http://irep.iium.edu.my/69761/19/69761%20The%20impact%20of%20scaling%20on%20single%20event%20upset%20in%206T%20and%2012T.pdf http://irep.iium.edu.my/69761/2/69761_The%20impact%20of%20scaling%20on%20single%20event%20upset_scopus.pdf
first_indexed	2023-09-18T21:39:01Z
last_indexed	2023-09-18T21:39:01Z
_version_	1777413014698328064

The impact of scaling on single event upset in 6T and 12T SRAMs from 130 to 22 nm CMOS technology

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