The impact of scaling on single event upset in 6T and 12T SRAMs from 130 to 22 nm CMOS technology
As transistor sizes scale down to nanometres dimensions, CMOS circuits become more sensitive to radiation. High-performance static random access memory (SRAM) cells are prone to radiation-induced single event upsets (SEU) which come from the natural space environment. The SEU generates a soft error...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English English |
| Published: |
Taylor & Francis
2018
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| Subjects: | |
| Online Access: | http://irep.iium.edu.my/69761/ http://irep.iium.edu.my/69761/ http://irep.iium.edu.my/69761/ http://irep.iium.edu.my/69761/19/69761%20The%20impact%20of%20scaling%20on%20single%20event%20upset%20in%206T%20and%2012T.pdf http://irep.iium.edu.my/69761/2/69761_The%20impact%20of%20scaling%20on%20single%20event%20upset_scopus.pdf |
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http://irep.iium.edu.my/69761/http://irep.iium.edu.my/69761/
http://irep.iium.edu.my/69761/
http://irep.iium.edu.my/69761/19/69761%20The%20impact%20of%20scaling%20on%20single%20event%20upset%20in%206T%20and%2012T.pdf
http://irep.iium.edu.my/69761/2/69761_The%20impact%20of%20scaling%20on%20single%20event%20upset_scopus.pdf