A new power efficient high performance interconnection network for many-core processors

Next generation high performance computing will most likely depend on the massively parallel computers. The overall performance of a massively parallel computer system is heavily affected by the interconnection network and its processing nodes. Continuing advances in VLSI technologies promise to del...

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Main Authors:	Al Faisal, Faiz, Rahman, M.M. Hafizur, Inoguchi, Yasushi
Format:	Article
Language:	English English English
Published:	Elsevier 2017
Subjects:	TK7800 Electronics. Computer engineering. Computer hardware. Photoelectronic devices TK7885 Computer engineering
Online Access:	http://irep.iium.edu.my/54364/ http://irep.iium.edu.my/54364/ http://irep.iium.edu.my/54364/ http://irep.iium.edu.my/54364/1/JPDC_3DTTN_Pub.pdf http://irep.iium.edu.my/54364/7/54364-A%20new%20power%20efficient%20high%20performance%20interconnection%20network%20for%20many-core%20processors_SCOPUS.pdf http://irep.iium.edu.my/54364/13/54364_A%20new%20power%20efficient%20high%20performance_WOS.pdf

id	iium-54364
recordtype	eprints
spelling	iium-543642018-03-28T02:39:30Z http://irep.iium.edu.my/54364/ A new power efficient high performance interconnection network for many-core processors Al Faisal, Faiz Rahman, M.M. Hafizur Inoguchi, Yasushi TK7800 Electronics. Computer engineering. Computer hardware. Photoelectronic devices TK7885 Computer engineering Next generation high performance computing will most likely depend on the massively parallel computers. The overall performance of a massively parallel computer system is heavily affected by the interconnection network and its processing nodes. Continuing advances in VLSI technologies promise to deliver more power to individual nodes. However, the on-chip interconnection networks consume up to 50% of the total chip power and off-chip bandwidth is limited to the maximum number of possible out going physical links. In addition, the long wiring and low performance of communication network overwhelm the benefit of parallel computer system whereas it increases total cost. In this paper, we propose a new interconnection network that reduces the problems of high power consumption, long wiring length and low bandwidth issues.We have measured the static network performance and required power consumption of our proposed ‘3D-TESH’ interconnection network and compared the performance with other networks at different levels of hierarchy such as inter-chips, inter-nodes and inter-cabinets. 3D-TESH network has achieved about 52.08% better diameter and about 45.71% better average distance than the 3D-Torus network with 12.61% less router power usage at on-chip level. Furthermore, 3D-TESH requires about 41% less router power usage than 5D-Torus at the on-chip level. Elsevier 2017-03 Article PeerReviewed application/pdf en http://irep.iium.edu.my/54364/1/JPDC_3DTTN_Pub.pdf application/pdf en http://irep.iium.edu.my/54364/7/54364-A%20new%20power%20efficient%20high%20performance%20interconnection%20network%20for%20many-core%20processors_SCOPUS.pdf application/pdf en http://irep.iium.edu.my/54364/13/54364_A%20new%20power%20efficient%20high%20performance_WOS.pdf Al Faisal, Faiz and Rahman, M.M. Hafizur and Inoguchi, Yasushi (2017) A new power efficient high performance interconnection network for many-core processors. Journal of Parallel Distributed Computing, 101. pp. 92-102. ISSN 0743-7315 E-ISSN 1096-0848 https://www.sciencedirect.com/science/article/pii/S0743731516301629 10.1016/j.jpdc.2016.11.007
repository_type	Digital Repository
institution_category	Local University
institution	International Islamic University Malaysia
building	IIUM Repository
collection	Online Access
language	English English English
topic	TK7800 Electronics. Computer engineering. Computer hardware. Photoelectronic devices TK7885 Computer engineering
spellingShingle	TK7800 Electronics. Computer engineering. Computer hardware. Photoelectronic devices TK7885 Computer engineering Al Faisal, Faiz Rahman, M.M. Hafizur Inoguchi, Yasushi A new power efficient high performance interconnection network for many-core processors
description	Next generation high performance computing will most likely depend on the massively parallel computers. The overall performance of a massively parallel computer system is heavily affected by the interconnection network and its processing nodes. Continuing advances in VLSI technologies promise to deliver more power to individual nodes. However, the on-chip interconnection networks consume up to 50% of the total chip power and off-chip bandwidth is limited to the maximum number of possible out going physical links. In addition, the long wiring and low performance of communication network overwhelm the benefit of parallel computer system whereas it increases total cost. In this paper, we propose a new interconnection network that reduces the problems of high power consumption, long wiring length and low bandwidth issues.We have measured the static network performance and required power consumption of our proposed ‘3D-TESH’ interconnection network and compared the performance with other networks at different levels of hierarchy such as inter-chips, inter-nodes and inter-cabinets. 3D-TESH network has achieved about 52.08% better diameter and about 45.71% better average distance than the 3D-Torus network with 12.61% less router power usage at on-chip level. Furthermore, 3D-TESH requires about 41% less router power usage than 5D-Torus at the on-chip level.
format	Article
author	Al Faisal, Faiz Rahman, M.M. Hafizur Inoguchi, Yasushi
author_facet	Al Faisal, Faiz Rahman, M.M. Hafizur Inoguchi, Yasushi
author_sort	Al Faisal, Faiz
title	A new power efficient high performance interconnection network for many-core processors
title_short	A new power efficient high performance interconnection network for many-core processors
title_full	A new power efficient high performance interconnection network for many-core processors
title_fullStr	A new power efficient high performance interconnection network for many-core processors
title_full_unstemmed	A new power efficient high performance interconnection network for many-core processors
title_sort	new power efficient high performance interconnection network for many-core processors
publisher	Elsevier
publishDate	2017
url	http://irep.iium.edu.my/54364/ http://irep.iium.edu.my/54364/ http://irep.iium.edu.my/54364/ http://irep.iium.edu.my/54364/1/JPDC_3DTTN_Pub.pdf http://irep.iium.edu.my/54364/7/54364-A%20new%20power%20efficient%20high%20performance%20interconnection%20network%20for%20many-core%20processors_SCOPUS.pdf http://irep.iium.edu.my/54364/13/54364_A%20new%20power%20efficient%20high%20performance_WOS.pdf
first_indexed	2023-09-18T21:16:55Z
last_indexed	2023-09-18T21:16:55Z
_version_	1777411623810498560

A new power efficient high performance interconnection network for many-core processors

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