FPGA implementation of multiplier for floating-point numbers based on IEEE 754-2008 standard
This paper illustrates designing and implementation process of floating point multiplier on Field Programmable Gate Array (FPGA). Floating-point operations are used in many fields like, digital signal processing, digital image processing, multimedia data analysis, etc. Implementation of fl...
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Journal of Communications Technology, Electronics and Computer Science
2015
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| Online Access: | http://irep.iium.edu.my/45503/ http://irep.iium.edu.my/45503/ http://irep.iium.edu.my/45503/1/2-50-1-PB.pdf |
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iium-455032017-03-06T08:24:51Z http://irep.iium.edu.my/45503/ FPGA implementation of multiplier for floating-point numbers based on IEEE 754-2008 standard Shyamsi, M. Ibrahimy, Muhammad Ibn Motakabber, S. M. A. Ahsan, M. R. T Technology (General) This paper illustrates designing and implementation process of floating point multiplier on Field Programmable Gate Array (FPGA). Floating-point operations are used in many fields like, digital signal processing, digital image processing, multimedia data analysis, etc. Implementation of floating-point multiplication is handy and easy for high level language. However, it is a challenging task to implement a floating-point multiplication in hardware level or in low level language due to the complexity of algorithms. A top-down approach has been applied for the prototyping of IEEE 754-2008 standard floating-point multiplier module using Verilog Hardware Description Language (HDL). Electronic Design Automation (EDA) tool of Altera Quartus II has been used for floating-point multiplier. The hardware implementation has been done by downloading the Verilog code onto Altera DE2 FPGA development board and found a satisfactory performance. Journal of Communications Technology, Electronics and Computer Science 2015-10 Article PeerReviewed application/pdf en http://irep.iium.edu.my/45503/1/2-50-1-PB.pdf Shyamsi, M. and Ibrahimy, Muhammad Ibn and Motakabber, S. M. A. and Ahsan, M. R. (2015) FPGA implementation of multiplier for floating-point numbers based on IEEE 754-2008 standard. Journal of Communications Technology, Electronics and Computer Science, 1. pp. 1-6. ISSN 2457-905X http://jctecs.com/index.php/com/index |
| repository_type |
Digital Repository |
| institution_category |
Local University |
| institution |
International Islamic University Malaysia |
| building |
IIUM Repository |
| collection |
Online Access |
| language |
English |
| topic |
T Technology (General) |
| spellingShingle |
T Technology (General) Shyamsi, M. Ibrahimy, Muhammad Ibn Motakabber, S. M. A. Ahsan, M. R. FPGA implementation of multiplier for floating-point numbers based on IEEE 754-2008 standard |
| description |
This paper illustrates designing and
implementation process of floating point multiplier on Field
Programmable Gate Array (FPGA). Floating-point operations
are used in many fields like, digital signal processing, digital
image processing, multimedia data analysis, etc. Implementation
of floating-point multiplication is handy and easy for high level
language. However, it is a challenging task to implement a
floating-point multiplication in hardware level or in low level
language due to the complexity of algorithms. A top-down
approach has been applied for the prototyping of IEEE 754-2008
standard floating-point multiplier module using Verilog
Hardware Description Language (HDL). Electronic Design
Automation (EDA) tool of Altera Quartus II has been used for
floating-point multiplier. The hardware implementation has been
done by downloading the Verilog code onto Altera DE2 FPGA
development board and found a satisfactory performance. |
| format |
Article |
| author |
Shyamsi, M. Ibrahimy, Muhammad Ibn Motakabber, S. M. A. Ahsan, M. R. |
| author_facet |
Shyamsi, M. Ibrahimy, Muhammad Ibn Motakabber, S. M. A. Ahsan, M. R. |
| author_sort |
Shyamsi, M. |
| title |
FPGA implementation of multiplier for floating-point numbers based on IEEE 754-2008 standard |
| title_short |
FPGA implementation of multiplier for floating-point numbers based on IEEE 754-2008 standard |
| title_full |
FPGA implementation of multiplier for floating-point numbers based on IEEE 754-2008 standard |
| title_fullStr |
FPGA implementation of multiplier for floating-point numbers based on IEEE 754-2008 standard |
| title_full_unstemmed |
FPGA implementation of multiplier for floating-point numbers based on IEEE 754-2008 standard |
| title_sort |
fpga implementation of multiplier for floating-point numbers based on ieee 754-2008 standard |
| publisher |
Journal of Communications Technology, Electronics and Computer Science |
| publishDate |
2015 |
| url |
http://irep.iium.edu.my/45503/ http://irep.iium.edu.my/45503/ http://irep.iium.edu.my/45503/1/2-50-1-PB.pdf |
| first_indexed |
2023-09-18T21:04:45Z |
| last_indexed |
2023-09-18T21:04:45Z |
| _version_ |
1777410858597482496 |