Design of a high-speed, reconfigurable digital rank order filter
A new architecture to realize a modular, high speed, reconfigurable, digital Rank Order Filter (ROF) is presented in this paper. A bit-level algorithm by Kar and Pradhan has been modified in this work to implement the proposed ROF. Using the proposed digital rank selection circuit it is possible to...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
IIUM Press
2009
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| Subjects: | |
| Online Access: | http://irep.iium.edu.my/4496/ http://irep.iium.edu.my/4496/ http://irep.iium.edu.my/4496/1/Design_of_a_high-speed%2C_reconfigurable_digital_rank_order_filter.pdf |
| Summary: | A new architecture to realize a modular, high speed, reconfigurable, digital Rank Order Filter (ROF) is presented in this paper. A bit-level algorithm by Kar and Pradhan has been modified in this work to implement the proposed ROF. Using the proposed digital rank selection circuit it is possible to find the element of a certain rank in a given sequence of N elements in each window in M steps, where M is the number of bits used in binary representation for the elements of the sequence. The size of the proposed ROF increases only linearly with the number of samples in each window to be ranked. The proposed ROF is also modular in nature, which means function of each part of the ROF is well defined and so the circuit can be easily expandable for larger window size. The proposed ROF has been implemented in FGPA and post-fit simulation results are presented in this paper. HSPICE simulation of the proposed ROF is also done for 0.18µm CMOS process. |
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