A Bayesian network-based framework with Constraint Satisfaction Problem (CSP) formulations for FPGA system design

A Bayesian network-based framework with Constraint Satisfaction Problem (CSP) formulations for FPGA system design

In recent years, there has been a growing interest in IP-reuse for SoCs in order to bridge the gap between the silicon capacity and the design productivity. This research work investigates how our proposed methodology can be used to partition and schedule a JPEG encoder IP core onto an FPGA. We will...

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Bibliographic Details
Main Authors: Azman, Amelia Wong, Bigdeli, Abbas, Mohd Mustafah, Yasir, Biglari-Abhari, Morteza, Lovell, Brian
Format: Conference or Workshop Item
Language:English
Published: 2010
Subjects:
T Technology (General)
Online Access:http://irep.iium.edu.my/28300/
http://irep.iium.edu.my/28300/
http://irep.iium.edu.my/28300/1/A_Bayesian_network-based_framework_with_Constraint_Satisfaction_Problem_%28CSP%29_formulations_for_FPGA_system_design.pdf

Internet

http://irep.iium.edu.my/28300/
http://irep.iium.edu.my/28300/
http://irep.iium.edu.my/28300/1/A_Bayesian_network-based_framework_with_Constraint_Satisfaction_Problem_%28CSP%29_formulations_for_FPGA_system_design.pdf

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