Design of a multiple valued logic analog to digital converter using 0.13μm CMOS process
The interconnect and increasing chip density is still poses major threats to the continued development of large scale binary integrated systems and implementation in VLSI using traditional binary logic system. The design and simulation of a Multiple Valued Logic (MVL) Analog-to-Digital Converter (...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Academic Information Press
2012
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| Subjects: | |
| Online Access: | http://irep.iium.edu.my/24248/ http://irep.iium.edu.my/24248/ http://irep.iium.edu.my/24248/1/Journal_SSDR.pdf |
| Summary: | The interconnect and increasing chip density is still poses major threats to the continued development of
large scale binary integrated systems and implementation in VLSI using traditional binary logic system.
The design and simulation of a Multiple Valued Logic (MVL) Analog-to-Digital Converter (ADC) circuit is
presented in this paper. The ADC generates multi-valued logic outputs rather than the conventional binary
output system. The design implements pipeline ADC architecture and is simulated using the model
parameters for a standard 0.13μm CMOS process. The performance analysis of the design shows desirable
qualities in terms of response, low power consumption, and a sampling rate of 500kz at a supply voltage of
1.3 V. The ADC design is suitable for the needs of mixed-signal integrated circuit design and implemented
as a conversion circuit for systems based on multi valued logic design. |
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