Design of a multiple valued logic analog to digital converter using 0.13μm CMOS process
The interconnect and increasing chip density is still poses major threats to the continued development of large scale binary integrated systems and implementation in VLSI using traditional binary logic system. The design and simulation of a Multiple Valued Logic (MVL) Analog-to-Digital Converter (...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Academic Information Press
2012
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| Subjects: | |
| Online Access: | http://irep.iium.edu.my/24248/ http://irep.iium.edu.my/24248/ http://irep.iium.edu.my/24248/1/Journal_SSDR.pdf |