An Experimental Study Of Combinational Logic Circuit Minimization Using Firefly Algorithm

Combinatorial logic circuit minimization is usualy done using Karnaugh’s Map or Bolean equation. This paper presents an aplication of Firefly Algorithm to design combinational logic circuit in which the objective function is to minimize the total number of gates used. Then, the algorithm is benchmar...

Full description

Bibliographic Details
Main Authors:	Aznilnda, Zainodin, Aida Khairunisa, Ab. Kadir, M. Nasir, Ayob, Ahmad Fariz, Hasan, Amar Faiz, Zainal Abidin, Fazlinashatul Suhaidah, Zahid, Hazriq Izuan, Jafar, Ismail, Mohd Khairuddin
Format:	Article
Language:	English
Published:	2014
Subjects:	TS Manufactures
Online Access:	http://umpir.ump.edu.my/id/eprint/7831/ http://umpir.ump.edu.my/id/eprint/7831/1/An_Experimental_Study_Of_Combinational_Logic_Circuit_Minimization_Using_Firefly_Algorithm.pdf

id	ump-7831
recordtype	eprints
spelling	ump-78312018-02-28T03:58:01Z http://umpir.ump.edu.my/id/eprint/7831/ An Experimental Study Of Combinational Logic Circuit Minimization Using Firefly Algorithm Aznilnda, Zainodin Aida Khairunisa, Ab. Kadir M. Nasir, Ayob Ahmad Fariz, Hasan Amar Faiz, Zainal Abidin Fazlinashatul Suhaidah, Zahid Hazriq Izuan, Jafar Ismail, Mohd Khairuddin TS Manufactures Combinatorial logic circuit minimization is usualy done using Karnaugh’s Map or Bolean equation. This paper presents an aplication of Firefly Algorithm to design combinational logic circuit in which the objective function is to minimize the total number of gates used. Then, the algorithm is benchmarked with other literatures. Result indicates that it able to find optimal solution but further analysis is required for a more complex combinatorial ogic circuit minimization 2014 Article PeerReviewed application/pdf en http://umpir.ump.edu.my/id/eprint/7831/1/An_Experimental_Study_Of_Combinational_Logic_Circuit_Minimization_Using_Firefly_Algorithm.pdf Aznilnda, Zainodin and Aida Khairunisa, Ab. Kadir and M. Nasir, Ayob and Ahmad Fariz, Hasan and Amar Faiz, Zainal Abidin and Fazlinashatul Suhaidah, Zahid and Hazriq Izuan, Jafar and Ismail, Mohd Khairuddin (2014) An Experimental Study Of Combinational Logic Circuit Minimization Using Firefly Algorithm. Coloquium on Robotics, Unmaned Systems And Cybernetics 2014 (CRUSC 2014). pp. 17-21.
repository_type	Digital Repository
institution_category	Local University
institution	Universiti Malaysia Pahang
building	UMP Institutional Repository
collection	Online Access
language	English
topic	TS Manufactures
spellingShingle	TS Manufactures Aznilnda, Zainodin Aida Khairunisa, Ab. Kadir M. Nasir, Ayob Ahmad Fariz, Hasan Amar Faiz, Zainal Abidin Fazlinashatul Suhaidah, Zahid Hazriq Izuan, Jafar Ismail, Mohd Khairuddin An Experimental Study Of Combinational Logic Circuit Minimization Using Firefly Algorithm
description	Combinatorial logic circuit minimization is usualy done using Karnaugh’s Map or Bolean equation. This paper presents an aplication of Firefly Algorithm to design combinational logic circuit in which the objective function is to minimize the total number of gates used. Then, the algorithm is benchmarked with other literatures. Result indicates that it able to find optimal solution but further analysis is required for a more complex combinatorial ogic circuit minimization
format	Article
author	Aznilnda, Zainodin Aida Khairunisa, Ab. Kadir M. Nasir, Ayob Ahmad Fariz, Hasan Amar Faiz, Zainal Abidin Fazlinashatul Suhaidah, Zahid Hazriq Izuan, Jafar Ismail, Mohd Khairuddin
author_facet	Aznilnda, Zainodin Aida Khairunisa, Ab. Kadir M. Nasir, Ayob Ahmad Fariz, Hasan Amar Faiz, Zainal Abidin Fazlinashatul Suhaidah, Zahid Hazriq Izuan, Jafar Ismail, Mohd Khairuddin
author_sort	Aznilnda, Zainodin
title	An Experimental Study Of Combinational Logic Circuit Minimization Using Firefly Algorithm
title_short	An Experimental Study Of Combinational Logic Circuit Minimization Using Firefly Algorithm
title_full	An Experimental Study Of Combinational Logic Circuit Minimization Using Firefly Algorithm
title_fullStr	An Experimental Study Of Combinational Logic Circuit Minimization Using Firefly Algorithm
title_full_unstemmed	An Experimental Study Of Combinational Logic Circuit Minimization Using Firefly Algorithm
title_sort	experimental study of combinational logic circuit minimization using firefly algorithm
publishDate	2014
url	http://umpir.ump.edu.my/id/eprint/7831/ http://umpir.ump.edu.my/id/eprint/7831/1/An_Experimental_Study_Of_Combinational_Logic_Circuit_Minimization_Using_Firefly_Algorithm.pdf
first_indexed	2023-09-18T22:04:52Z
last_indexed	2023-09-18T22:04:52Z
_version_	1777414640763928576

An Experimental Study Of Combinational Logic Circuit Minimization Using Firefly Algorithm

Similar Items