A New Approach for Dimensional Optimization of Inverters in 6T-Static Random-Access Memory Cell Based on Silicon Nanowire Transistor

A New Approach for Dimensional Optimization of Inverters in 6T-Static Random-Access Memory Cell Based on Silicon Nanowire Transistor

This study explores dimensional optimization at different high logic-level voltages for six silicon nanowire transistor (SiNWT)-based static random-access memory (SRAM) cell. This study is the first to demonstrate diameter and length of nanowires with different logic voltage level (Vdd) optimization...

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Bibliographic Details
Main Author: Hashim, Yasir
Format: Article
Language:English
English
Published: American Scientific Publishers 2017
Subjects:
TK Electrical engineering. Electronics Nuclear engineering
Online Access:http://umpir.ump.edu.my/id/eprint/15045/
http://umpir.ump.edu.my/id/eprint/15045/
http://umpir.ump.edu.my/id/eprint/15045/
http://umpir.ump.edu.my/id/eprint/15045/1/16JNN-12608.pdf
http://umpir.ump.edu.my/id/eprint/15045/7/ftech-yasir-2017.pdf
id ump-15045
recordtype eprints
spelling ump-150452017-11-29T02:54:48Z http://umpir.ump.edu.my/id/eprint/15045/ A New Approach for Dimensional Optimization of Inverters in 6T-Static Random-Access Memory Cell Based on Silicon Nanowire Transistor Hashim, Yasir TK Electrical engineering. Electronics Nuclear engineering This study explores dimensional optimization at different high logic-level voltages for six silicon nanowire transistor (SiNWT)-based static random-access memory (SRAM) cell. This study is the first to demonstrate diameter and length of nanowires with different logic voltage level (Vdd) optimizations of nanoscale SiNWT-based SRAM cell. Noise margins and inflection voltage of butterfly characteristics are used as limiting factors in this optimization. Results indicate that optimization depends on nanowire dimensions and Vdd. The increase in Vdd from 1 V to 3 V tends to decrease the dimensions of the optimized nanowires but increases the current and power. SRAM using nanowire transistors must use Vdd of 2 or 2.5 V to produce SRAM with lower dimensions, inflection currents, and power consumption. American Scientific Publishers 2017-02 Article PeerReviewed application/pdf en http://umpir.ump.edu.my/id/eprint/15045/1/16JNN-12608.pdf application/pdf en http://umpir.ump.edu.my/id/eprint/15045/7/ftech-yasir-2017.pdf Hashim, Yasir (2017) A New Approach for Dimensional Optimization of Inverters in 6T-Static Random-Access Memory Cell Based on Silicon Nanowire Transistor. Journal of Nanoscience and Nanotechnology, 17 (2). pp. 1061-1067. ISSN 1533-4880 (Print); 1533-4899 (Online) https://doi.org/10.1166/jnn.2017.12608 doi: 10.1166/jnn.2017.12608
repository_type Digital Repository
institution_category Local University
institution Universiti Malaysia Pahang
building UMP Institutional Repository
collection Online Access
language English
English
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
Hashim, Yasir
A New Approach for Dimensional Optimization of Inverters in 6T-Static Random-Access Memory Cell Based on Silicon Nanowire Transistor
description This study explores dimensional optimization at different high logic-level voltages for six silicon nanowire transistor (SiNWT)-based static random-access memory (SRAM) cell. This study is the first to demonstrate diameter and length of nanowires with different logic voltage level (Vdd) optimizations of nanoscale SiNWT-based SRAM cell. Noise margins and inflection voltage of butterfly characteristics are used as limiting factors in this optimization. Results indicate that optimization depends on nanowire dimensions and Vdd. The increase in Vdd from 1 V to 3 V tends to decrease the dimensions of the optimized nanowires but increases the current and power. SRAM using nanowire transistors must use Vdd of 2 or 2.5 V to produce SRAM with lower dimensions, inflection currents, and power consumption.
format Article
author Hashim, Yasir
author_facet Hashim, Yasir
author_sort Hashim, Yasir
title A New Approach for Dimensional Optimization of Inverters in 6T-Static Random-Access Memory Cell Based on Silicon Nanowire Transistor
title_short A New Approach for Dimensional Optimization of Inverters in 6T-Static Random-Access Memory Cell Based on Silicon Nanowire Transistor
title_full A New Approach for Dimensional Optimization of Inverters in 6T-Static Random-Access Memory Cell Based on Silicon Nanowire Transistor
title_fullStr A New Approach for Dimensional Optimization of Inverters in 6T-Static Random-Access Memory Cell Based on Silicon Nanowire Transistor
title_full_unstemmed A New Approach for Dimensional Optimization of Inverters in 6T-Static Random-Access Memory Cell Based on Silicon Nanowire Transistor
title_sort new approach for dimensional optimization of inverters in 6t-static random-access memory cell based on silicon nanowire transistor
publisher American Scientific Publishers
publishDate 2017
url http://umpir.ump.edu.my/id/eprint/15045/
http://umpir.ump.edu.my/id/eprint/15045/
http://umpir.ump.edu.my/id/eprint/15045/
http://umpir.ump.edu.my/id/eprint/15045/1/16JNN-12608.pdf
http://umpir.ump.edu.my/id/eprint/15045/7/ftech-yasir-2017.pdf
first_indexed 2023-09-18T22:19:19Z
last_indexed 2023-09-18T22:19:19Z
_version_ 1777415549740908544

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