Design of large built-in self-test programmable logic arrays
This paper presents a way to optimize design of large built-in self-test (BIST) programmable logic arrays (PLAs). These PLAs can be tested at clock speed with function independent test set. Hardware overhead of the design is low compared to other techniques. In the design, test pattern generators...
| Main Authors: | , |
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| Format: | Article |
| Published: |
1993
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| Online Access: | http://journalarticle.ukm.my/1304/ http://journalarticle.ukm.my/1304/ |