Johari, M. A. (2015). Logical effort base adder circuits transistor sizing using constriction factor and mutative variants of particle swarm optimization algorithm / Muhammad Aiman Johari.
Chicago Style (17th ed.) CitationJohari, Muhammad Aiman. Logical Effort Base Adder Circuits Transistor Sizing Using Constriction Factor and Mutative Variants of Particle Swarm Optimization Algorithm / Muhammad Aiman Johari. 2015.
MLA (8th ed.) CitationJohari, Muhammad Aiman. Logical Effort Base Adder Circuits Transistor Sizing Using Constriction Factor and Mutative Variants of Particle Swarm Optimization Algorithm / Muhammad Aiman Johari. 2015.
Warning: These citations may not always be 100% accurate.