Inter-Processor Communication Performance of a Hierarchical Torus Network under Bit-Flip Traffic Patterns

Inter-Processor Communication Performance of a Hierarchical Torus Network under Bit-Flip Traffic Patterns

In this paper, we present a deadlock-free routing algorithm for the hierarchical torus network (HTN) using 2 virtual channels - 2 being the minimum number for dimension order routing - and evaluate the network's inter-processor communication performance under the bit-flip traffic pattern using...

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Main Authors: Rahman, M.M. Hafizur, Ghosh, Manas, Horiguchi, Susumu
Format: Conference or Workshop Item
Language:English
Published: 2006
Subjects:
TK Electrical engineering. Electronics Nuclear engineering
Online Access:http://irep.iium.edu.my/8227/
http://irep.iium.edu.my/8227/
http://irep.iium.edu.my/8227/1/ICECE_2006.pdf
id iium-8227
recordtype eprints
spelling iium-82272012-12-19T04:48:33Z http://irep.iium.edu.my/8227/ Inter-Processor Communication Performance of a Hierarchical Torus Network under Bit-Flip Traffic Patterns Rahman, M.M. Hafizur Ghosh, Manas Horiguchi, Susumu TK Electrical engineering. Electronics Nuclear engineering In this paper, we present a deadlock-free routing algorithm for the hierarchical torus network (HTN) using 2 virtual channels - 2 being the minimum number for dimension order routing - and evaluate the network's inter-processor communication performance under the bit-flip traffic pattern using the proposed routing algorithm. We evaluate the inter-processor communication performance of HTN, H3D-mesh, TESH, mesh, and torus network by computer simulation. It is shown that the inter-processor communication performance of the HTN is better than that of the H3D-mesh, TESH, mesh, and torus networks. 2006-12 Conference or Workshop Item PeerReviewed application/pdf en http://irep.iium.edu.my/8227/1/ICECE_2006.pdf Rahman, M.M. Hafizur and Ghosh, Manas and Horiguchi, Susumu (2006) Inter-Processor Communication Performance of a Hierarchical Torus Network under Bit-Flip Traffic Patterns. In: Electrical and Computer Engineering, 2006. ICECE '06. International Conference on , 19-21 Dec. 2006 , Dhaka, Bangladesh. http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4178532
repository_type Digital Repository
institution_category Local University
institution International Islamic University Malaysia
building IIUM Repository
collection Online Access
language English
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
Rahman, M.M. Hafizur
Ghosh, Manas
Horiguchi, Susumu
Inter-Processor Communication Performance of a Hierarchical Torus Network under Bit-Flip Traffic Patterns
description In this paper, we present a deadlock-free routing algorithm for the hierarchical torus network (HTN) using 2 virtual channels - 2 being the minimum number for dimension order routing - and evaluate the network's inter-processor communication performance under the bit-flip traffic pattern using the proposed routing algorithm. We evaluate the inter-processor communication performance of HTN, H3D-mesh, TESH, mesh, and torus network by computer simulation. It is shown that the inter-processor communication performance of the HTN is better than that of the H3D-mesh, TESH, mesh, and torus networks.
format Conference or Workshop Item
author Rahman, M.M. Hafizur
Ghosh, Manas
Horiguchi, Susumu
author_facet Rahman, M.M. Hafizur
Ghosh, Manas
Horiguchi, Susumu
author_sort Rahman, M.M. Hafizur
title Inter-Processor Communication Performance of a Hierarchical Torus Network under Bit-Flip Traffic Patterns
title_short Inter-Processor Communication Performance of a Hierarchical Torus Network under Bit-Flip Traffic Patterns
title_full Inter-Processor Communication Performance of a Hierarchical Torus Network under Bit-Flip Traffic Patterns
title_fullStr Inter-Processor Communication Performance of a Hierarchical Torus Network under Bit-Flip Traffic Patterns
title_full_unstemmed Inter-Processor Communication Performance of a Hierarchical Torus Network under Bit-Flip Traffic Patterns
title_sort inter-processor communication performance of a hierarchical torus network under bit-flip traffic patterns
publishDate 2006
url http://irep.iium.edu.my/8227/
http://irep.iium.edu.my/8227/
http://irep.iium.edu.my/8227/1/ICECE_2006.pdf
first_indexed 2023-09-18T20:17:53Z
last_indexed 2023-09-18T20:17:53Z
_version_ 1777407910217777152

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