Efficient cache replacement policy for minimizing error rate in L2-STT-MRAM caches
In recent times, various challenges have been encountered in the design and development of SRAM cache which consequently has led to a design where memory cell technologies are converted into on-chip embedded caches. The current research statistics for cache designing reveals that Spin Torque Transfe...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English English |
| Published: |
Inderscience Publishers
2018
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| Subjects: | |
| Online Access: | http://irep.iium.edu.my/66902/ http://irep.iium.edu.my/66902/ http://irep.iium.edu.my/66902/ http://irep.iium.edu.my/66902/30/66902%20Efficient%20cache%20replacement%20policy%20for%20minimising.pdf http://irep.iium.edu.my/66902/31/66902%20Efficient%20cache%20replacement%20policy%20for%20minimising%20SCOPUS.pdf |