Negative bias temperature instability characterization and lifetime evaluations of submicron pMOSFET
A major effect of different measurement delay in seconds is revealed through quasi DC Stress Measure Stress experiments. We found that different delay of measurements in seconds contributed to different stress time needed to achieve target 10% degradation of Vth. The longer delay, the more time...
| Main Authors: | , , , , , , , |
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| Format: | Conference or Workshop Item |
| Language: | English English |
| Published: |
IEEE
2017
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| Subjects: | |
| Online Access: | http://irep.iium.edu.my/62886/ http://irep.iium.edu.my/62886/ http://irep.iium.edu.my/62886/ http://irep.iium.edu.my/62886/1/62886%20Negative%20Bias%20Temperature%20Instability%20Characterization.pdf http://irep.iium.edu.my/62886/2/62886%20Negative%20Bias%20Temperature%20Instability%20SCOPUS.pdf |
| Summary: | A major effect of different measurement delay in
seconds is revealed through quasi DC Stress Measure Stress
experiments. We found that different delay of measurements in
seconds contributed to different stress time needed to achieve
target 10% degradation of Vth. The longer delay, the more time
needed for the device to achieve 10% degradation of Vth. The effect
on NBTI degradation is shown to be reliant on stress conditions
(stress voltage, temperature) and device architecture (gate
dimensions, gate oxide thickness). The NBTI lifetime was
predicted by extrapolating lifetime to the nominal operating
voltage from Time-to-Fail versus stress bias and oxide electric field
plots. Both plots show that the lifetime of degradation parameter
of Vth is lower compared to the lifetime of degradation parameter
of Idsat. |
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