Design and analysis of a boosted pierce oscillator using MEMS SAW resonators
This paper highlights the design and analysis of a pierce oscillator circuit for CMOS MEMS surface acoustic wave resonators. The boosted pierce topology using two, three-stage cascode amplifiers provides sufficient gain to counteract the high insertion losses of - 65 dB at 1.3 GHz of the SAW resonat...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English English English English |
| Published: |
Springer Berlin Heidelberg
2018
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| Subjects: | |
| Online Access: | http://irep.iium.edu.my/59902/ http://irep.iium.edu.my/59902/ http://irep.iium.edu.my/59902/ http://irep.iium.edu.my/59902/1/59902_Design%20and%20analysis%20of%20a%20boosted_SCOPUS.pdf http://irep.iium.edu.my/59902/2/59902_Design%20and%20analysis%20of%20a%20boosted_MYRA.pdf http://irep.iium.edu.my/59902/13/59902_Design%20and%20analysis.pdf http://irep.iium.edu.my/59902/19/59902_Design%20and%20analysis%20of%20a%20boosted%20pierce%20oscillator%20using%20MEMS%20SAW%20resonators_WOS.pdf |
| Summary: | This paper highlights the design and analysis of a pierce oscillator circuit for CMOS MEMS surface acoustic wave resonators. The boosted pierce topology using two, three-stage cascode amplifiers provides sufficient gain to counteract the high insertion losses of - 65 dB at 1.3 GHz of the SAW resonator. For accurate prediction of the oscillator’s performance before fabrication, circuit design utilized touchstone S2P measurement results of the MEMS SAW resonator, which provides better results compared to the conventional method of using equivalent circuit simulations. This circuit was designed using Silterra’s 0.13 lm CMOS process. It has low power consumption of 1.52 mW with high voltage swing 0.10–0.99 V. All simulations were conducted using Cadence Design Systems and results indicate that phase noise of 92.63 dBc at 1 MHz. |
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