An efficient cache replacement algorithm for minimizing the error rate in L2-STT-MRAM caches

In the recent times, various challenges are being encountered during SRAM cache design and development which lead to a situation of converting the memory cell technologies into on-chip embedded caches. The current research statistics towards cache designing reveals that Spin Torque Transfer Magneti...

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Main Authors:	Olanrewaju, Rashidah Funke, Asifa Mehraj Baba, Asifa Mehraj, Khan, Burhan Ul Islam, Yaacob, Mashkuri, Azman, Amelia Wong, Mir, Mohammad Shuaib
Format:	Conference or Workshop Item
Language:	English English
Published:	IEEE 2017
Subjects:	TK7885 Computer engineering
Online Access:	http://irep.iium.edu.my/55972/ http://irep.iium.edu.my/55972/ http://irep.iium.edu.my/55972/ http://irep.iium.edu.my/55972/7/55972%20An%20efficient%20cache%20replacement%20algorithm.pdf http://irep.iium.edu.my/55972/8/55972%20An%20efficient%20cache%20replacement%20algorithm%20SCOPUS.pdf

id	iium-55972
recordtype	eprints
spelling	iium-559722018-12-07T07:40:15Z http://irep.iium.edu.my/55972/ An efficient cache replacement algorithm for minimizing the error rate in L2-STT-MRAM caches Olanrewaju, Rashidah Funke Asifa Mehraj Baba, Asifa Mehraj Khan, Burhan Ul Islam Yaacob, Mashkuri Azman, Amelia Wong Mir, Mohammad Shuaib TK7885 Computer engineering In the recent times, various challenges are being encountered during SRAM cache design and development which lead to a situation of converting the memory cell technologies into on-chip embedded caches. The current research statistics towards cache designing reveals that Spin Torque Transfer Magnetic RAMs, preferably termed as STT-MRAMs has become one of the most promising areas in the field of memory chip design. Hence, it gained a lot of attention from the researchers due to its dynamic direct map and data access policies for reducing the average cost i.e. time and energy optimization. Instead of having efficient main memory access capability, STTMRAMs suffer due to high error rate caused during stochastic switching in write operations. Cache replacement algorithms play a significant role in minimizing the error rate in write operations. The proposed study aims to offer a theoretical and analytical modeling of an efficient cache replacement scheme to overcome the error as mentioned above in L2-STT-MRAM caches. The performance analysis of the proposed algorithm ensures its effectiveness in reducing the error rate and cost overheads as compared to the conventional LRU technique implemented on SRAM cells. IEEE 2017-04-27 Conference or Workshop Item PeerReviewed application/pdf en http://irep.iium.edu.my/55972/7/55972%20An%20efficient%20cache%20replacement%20algorithm.pdf application/pdf en http://irep.iium.edu.my/55972/8/55972%20An%20efficient%20cache%20replacement%20algorithm%20SCOPUS.pdf Olanrewaju, Rashidah Funke and Asifa Mehraj Baba, Asifa Mehraj and Khan, Burhan Ul Islam and Yaacob, Mashkuri and Azman, Amelia Wong and Mir, Mohammad Shuaib (2017) An efficient cache replacement algorithm for minimizing the error rate in L2-STT-MRAM caches. In: 2016 Fourth International Conference on Parallel, Distributed and Grid Computing(PDGC), 22nd-24th December 2016, Jaypee, India. https://ieeexplore.ieee.org/document/7913229 10.1109/PDGC.2016.7913229
repository_type	Digital Repository
institution_category	Local University
institution	International Islamic University Malaysia
building	IIUM Repository
collection	Online Access
language	English English
topic	TK7885 Computer engineering
spellingShingle	TK7885 Computer engineering Olanrewaju, Rashidah Funke Asifa Mehraj Baba, Asifa Mehraj Khan, Burhan Ul Islam Yaacob, Mashkuri Azman, Amelia Wong Mir, Mohammad Shuaib An efficient cache replacement algorithm for minimizing the error rate in L2-STT-MRAM caches
description	In the recent times, various challenges are being encountered during SRAM cache design and development which lead to a situation of converting the memory cell technologies into on-chip embedded caches. The current research statistics towards cache designing reveals that Spin Torque Transfer Magnetic RAMs, preferably termed as STT-MRAMs has become one of the most promising areas in the field of memory chip design. Hence, it gained a lot of attention from the researchers due to its dynamic direct map and data access policies for reducing the average cost i.e. time and energy optimization. Instead of having efficient main memory access capability, STTMRAMs suffer due to high error rate caused during stochastic switching in write operations. Cache replacement algorithms play a significant role in minimizing the error rate in write operations. The proposed study aims to offer a theoretical and analytical modeling of an efficient cache replacement scheme to overcome the error as mentioned above in L2-STT-MRAM caches. The performance analysis of the proposed algorithm ensures its effectiveness in reducing the error rate and cost overheads as compared to the conventional LRU technique implemented on SRAM cells.
format	Conference or Workshop Item
author	Olanrewaju, Rashidah Funke Asifa Mehraj Baba, Asifa Mehraj Khan, Burhan Ul Islam Yaacob, Mashkuri Azman, Amelia Wong Mir, Mohammad Shuaib
author_facet	Olanrewaju, Rashidah Funke Asifa Mehraj Baba, Asifa Mehraj Khan, Burhan Ul Islam Yaacob, Mashkuri Azman, Amelia Wong Mir, Mohammad Shuaib
author_sort	Olanrewaju, Rashidah Funke
title	An efficient cache replacement algorithm for minimizing the error rate in L2-STT-MRAM caches
title_short	An efficient cache replacement algorithm for minimizing the error rate in L2-STT-MRAM caches
title_full	An efficient cache replacement algorithm for minimizing the error rate in L2-STT-MRAM caches
title_fullStr	An efficient cache replacement algorithm for minimizing the error rate in L2-STT-MRAM caches
title_full_unstemmed	An efficient cache replacement algorithm for minimizing the error rate in L2-STT-MRAM caches
title_sort	efficient cache replacement algorithm for minimizing the error rate in l2-stt-mram caches
publisher	IEEE
publishDate	2017
url	http://irep.iium.edu.my/55972/ http://irep.iium.edu.my/55972/ http://irep.iium.edu.my/55972/ http://irep.iium.edu.my/55972/7/55972%20An%20efficient%20cache%20replacement%20algorithm.pdf http://irep.iium.edu.my/55972/8/55972%20An%20efficient%20cache%20replacement%20algorithm%20SCOPUS.pdf
first_indexed	2023-09-18T21:18:59Z
last_indexed	2023-09-18T21:18:59Z
_version_	1777411753657761792

An efficient cache replacement algorithm for minimizing the error rate in L2-STT-MRAM caches

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