Effect of single event upset on 6T and 12T 32NM CMOS SRAMs circuit

Effect of single event upset on 6T and 12T 32NM CMOS SRAMs circuit

Static random access memory cells (SRAM) are high-speed semiconductor memory that uses flip-flop to store each bit. Over the years, technology scaling of complementary metaloxide semiconductor (CMOS) devices has also resulted in the scaling of SRAM using minimum-size transistors. As transistor si...

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Main Authors: Yusop, Nur Syafiqah, Mahmud, Manzar, Nordin, Anis Nurashikin, Hasbullah, Nurul Fadzlin
Format: Conference or Workshop Item
Language:English
Published: Penerbit UMT, Universiti Malaysia Terengganu (UMT) 2016
Subjects:
TK Electrical engineering. Electronics Nuclear engineering
Online Access:http://irep.iium.edu.my/51579/
http://irep.iium.edu.my/51579/
http://irep.iium.edu.my/51579/1/51579_Effect%20of%20single%20event.pdf
id iium-51579
recordtype eprints
spelling iium-515792017-01-10T08:18:06Z http://irep.iium.edu.my/51579/ Effect of single event upset on 6T and 12T 32NM CMOS SRAMs circuit Yusop, Nur Syafiqah Mahmud, Manzar Nordin, Anis Nurashikin Hasbullah, Nurul Fadzlin TK Electrical engineering. Electronics Nuclear engineering Static random access memory cells (SRAM) are high-speed semiconductor memory that uses flip-flop to store each bit. Over the years, technology scaling of complementary metaloxide semiconductor (CMOS) devices has also resulted in the scaling of SRAM using minimum-size transistors. As transistor sizes scale down towards lower two-digit nanometer dimensions, CMOS circuits become more sensitive to radiations effects. High performances and high-density SRAMs are prone to radiation-induced single event upsets (SEU) which are dominated by secondary ions generated by nuclear collision events in the chip. The SEU generates are a soft error in transistor due to the strike of an ionizing particle. Thus, this paper compares the endurance of 12T SRAM and 6T SRAM circuit on 32nm CMOS technology towards SEU which is caused by the heavy ion impact with different Linear Energy Transfer characteristic (LET). This paper discussed the effect of LET towards drain node of NMOS and PMOS transistor for both 6T and 12T SRAM. The simulation results and analyses show that 6T SRAM circuit is vulnerable to SEU compared to 12T SRAM. Penerbit UMT, Universiti Malaysia Terengganu (UMT) 2016 Conference or Workshop Item PeerReviewed application/pdf en http://irep.iium.edu.my/51579/1/51579_Effect%20of%20single%20event.pdf Yusop, Nur Syafiqah and Mahmud, Manzar and Nordin, Anis Nurashikin and Hasbullah, Nurul Fadzlin (2016) Effect of single event upset on 6T and 12T 32NM CMOS SRAMs circuit. In: 13th Universiti Malaysia Terengganu International Annual Symposium on Sustainability Science and Management (UMTAS 2016), 13th-15th Dec. 2016, Kuala Terengganu, Terengganu. http://umtas2016.umt.edu.my/?page_id=210
repository_type Digital Repository
institution_category Local University
institution International Islamic University Malaysia
building IIUM Repository
collection Online Access
language English
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
Yusop, Nur Syafiqah
Mahmud, Manzar
Nordin, Anis Nurashikin
Hasbullah, Nurul Fadzlin
Effect of single event upset on 6T and 12T 32NM CMOS SRAMs circuit
description Static random access memory cells (SRAM) are high-speed semiconductor memory that uses flip-flop to store each bit. Over the years, technology scaling of complementary metaloxide semiconductor (CMOS) devices has also resulted in the scaling of SRAM using minimum-size transistors. As transistor sizes scale down towards lower two-digit nanometer dimensions, CMOS circuits become more sensitive to radiations effects. High performances and high-density SRAMs are prone to radiation-induced single event upsets (SEU) which are dominated by secondary ions generated by nuclear collision events in the chip. The SEU generates are a soft error in transistor due to the strike of an ionizing particle. Thus, this paper compares the endurance of 12T SRAM and 6T SRAM circuit on 32nm CMOS technology towards SEU which is caused by the heavy ion impact with different Linear Energy Transfer characteristic (LET). This paper discussed the effect of LET towards drain node of NMOS and PMOS transistor for both 6T and 12T SRAM. The simulation results and analyses show that 6T SRAM circuit is vulnerable to SEU compared to 12T SRAM.
format Conference or Workshop Item
author Yusop, Nur Syafiqah
Mahmud, Manzar
Nordin, Anis Nurashikin
Hasbullah, Nurul Fadzlin
author_facet Yusop, Nur Syafiqah
Mahmud, Manzar
Nordin, Anis Nurashikin
Hasbullah, Nurul Fadzlin
author_sort Yusop, Nur Syafiqah
title Effect of single event upset on 6T and 12T 32NM CMOS SRAMs circuit
title_short Effect of single event upset on 6T and 12T 32NM CMOS SRAMs circuit
title_full Effect of single event upset on 6T and 12T 32NM CMOS SRAMs circuit
title_fullStr Effect of single event upset on 6T and 12T 32NM CMOS SRAMs circuit
title_full_unstemmed Effect of single event upset on 6T and 12T 32NM CMOS SRAMs circuit
title_sort effect of single event upset on 6t and 12t 32nm cmos srams circuit
publisher Penerbit UMT, Universiti Malaysia Terengganu (UMT)
publishDate 2016
url http://irep.iium.edu.my/51579/
http://irep.iium.edu.my/51579/
http://irep.iium.edu.my/51579/1/51579_Effect%20of%20single%20event.pdf
first_indexed 2023-09-18T21:13:02Z
last_indexed 2023-09-18T21:13:02Z
_version_ 1777411379392675840

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