Fault tolerant hardware for high performance signal processing

The approach described in this paper uses an array of Field Programmable Gate Array (FPGA) devices to implement a fault tolerant hardware system that can be compared to the running of fault tolerant software on a traditional processor. Fault tolerance is achieved is achieved by using FPGA with on t...

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Main Authors:	Erdogan, S. S., Shaneyfelf, Ted, Geok, See Ng, Abdul Rahman, Abdul Wahab
Format:	Conference or Workshop Item
Language:	English
Published:	2008
Subjects:	T Technology (General)
Online Access:	http://irep.iium.edu.my/38157/ http://irep.iium.edu.my/38157/ http://irep.iium.edu.my/38157/1/Fault_Tolerant_Hardware_for_High_Performance_Signal_Processing.pdf

id	iium-38157
recordtype	eprints
spelling	iium-381572014-09-18T06:00:58Z http://irep.iium.edu.my/38157/ Fault tolerant hardware for high performance signal processing Erdogan, S. S. Shaneyfelf, Ted Geok, See Ng Abdul Rahman, Abdul Wahab T Technology (General) The approach described in this paper uses an array of Field Programmable Gate Array (FPGA) devices to implement a fault tolerant hardware system that can be compared to the running of fault tolerant software on a traditional processor. Fault tolerance is achieved is achieved by using FPGA with on the fly partial programmability feature. Major considerations while mapping to the FPGA includes the size of the area to be mapped and communication issues related to their communication. Area size selection is compared to the page size selection in Operating System Design. Communication issues between modules are compared to the software engineering paradigms dealing with module coupling, fan-in, fan-out and cohesiveness. Finally, the overhead associated with the downloading of the reconfiguration files is discussed. 2008 Conference or Workshop Item NonPeerReviewed application/pdf en http://irep.iium.edu.my/38157/1/Fault_Tolerant_Hardware_for_High_Performance_Signal_Processing.pdf Erdogan, S. S. and Shaneyfelf, Ted and Geok, See Ng and Abdul Rahman, Abdul Wahab (2008) Fault tolerant hardware for high performance signal processing. In: The Fourth Advanced International Conference on Telecommunications AICT '08, 8-13 June 2008, Athens, Greece. http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4545565
repository_type	Digital Repository
institution_category	Local University
institution	International Islamic University Malaysia
building	IIUM Repository
collection	Online Access
language	English
topic	T Technology (General)
spellingShingle	T Technology (General) Erdogan, S. S. Shaneyfelf, Ted Geok, See Ng Abdul Rahman, Abdul Wahab Fault tolerant hardware for high performance signal processing
description	The approach described in this paper uses an array of Field Programmable Gate Array (FPGA) devices to implement a fault tolerant hardware system that can be compared to the running of fault tolerant software on a traditional processor. Fault tolerance is achieved is achieved by using FPGA with on the fly partial programmability feature. Major considerations while mapping to the FPGA includes the size of the area to be mapped and communication issues related to their communication. Area size selection is compared to the page size selection in Operating System Design. Communication issues between modules are compared to the software engineering paradigms dealing with module coupling, fan-in, fan-out and cohesiveness. Finally, the overhead associated with the downloading of the reconfiguration files is discussed.
format	Conference or Workshop Item
author	Erdogan, S. S. Shaneyfelf, Ted Geok, See Ng Abdul Rahman, Abdul Wahab
author_facet	Erdogan, S. S. Shaneyfelf, Ted Geok, See Ng Abdul Rahman, Abdul Wahab
author_sort	Erdogan, S. S.
title	Fault tolerant hardware for high performance signal processing
title_short	Fault tolerant hardware for high performance signal processing
title_full	Fault tolerant hardware for high performance signal processing
title_fullStr	Fault tolerant hardware for high performance signal processing
title_full_unstemmed	Fault tolerant hardware for high performance signal processing
title_sort	fault tolerant hardware for high performance signal processing
publishDate	2008
url	http://irep.iium.edu.my/38157/ http://irep.iium.edu.my/38157/ http://irep.iium.edu.my/38157/1/Fault_Tolerant_Hardware_for_High_Performance_Signal_Processing.pdf
first_indexed	2023-09-18T20:54:47Z
last_indexed	2023-09-18T20:54:47Z
_version_	1777410231508140032

Fault tolerant hardware for high performance signal processing

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