Zero skew clock routing for fast clock tree generation
A Zero Skew Clock Routing Methodology has been developed to help design team speed up their clock tree generation process. The methodology works by breaking up the clock net into smaller partitions, then inserting clock buffers to drive each portion, and lastly, routing the connection from orig...
| Main Authors: | , , , , |
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| Format: | Conference or Workshop Item |
| Language: | English |
| Published: |
2008
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| Subjects: | |
| Online Access: | http://irep.iium.edu.my/36143/ http://irep.iium.edu.my/36143/ http://irep.iium.edu.my/36143/1/04564488.pdf |
| Summary: | A Zero Skew Clock Routing Methodology has been
developed to help design team speed up their clock tree
generation process. The methodology works by breaking up
the clock net into smaller partitions, then inserting clock
buffers to drive each portion, and lastly, routing the
connection from original clock source to each newly
inserted clock buffers with zero skew. A few Perl scripts
and a new Visual Basic based routing tool have been
developed to support the methodology implementation. The
routing algorithm used in this tool is based on the Exact
Zero Skew Routing Algorithm. The methodology has been
tested using a real design database and resulting in a
significant improvement in the through put time required to
complete the clock tree generation. This improvement is
attributed to the ability to generate clock tree on much
smaller portions of clock nets that supports of speeding up
the clock tree generation process in IC design. |
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