Hardware modeling of binary coded decimal adder in FPGA

There are insignificant relevant research works available which are involved with the Field Programmable Gate Array (FPGA) based hardware implementation of Binary Coded Decimal (BCD) adder. This is because, the FPGA based hardware realization is quiet new and still developing field of research....

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Main Authors:	Ibrahimy, Muhammad Ibn, Ahsan, Md. Rezwanul, Bambang Soeroso, Iksannurazmi
Format:	Article
Language:	English
Published:	World Scientific and Engineering Academy and Society 2012
Subjects:	T Technology (General)
Online Access:	http://irep.iium.edu.my/27422/ http://irep.iium.edu.my/27422/ http://irep.iium.edu.my/27422/1/Hardware_Modeling_of_Binary_Coded_Decimal_Adder_in_FPGA.pdf

id	iium-27422
recordtype	eprints
spelling	iium-274222012-12-14T00:10:44Z http://irep.iium.edu.my/27422/ Hardware modeling of binary coded decimal adder in FPGA Ibrahimy, Muhammad Ibn Ahsan, Md. Rezwanul Bambang Soeroso, Iksannurazmi T Technology (General) There are insignificant relevant research works available which are involved with the Field Programmable Gate Array (FPGA) based hardware implementation of Binary Coded Decimal (BCD) adder. This is because, the FPGA based hardware realization is quiet new and still developing field of research. The article illustrates the design and hardware modeling of a BCD adder. Among the types of adders, Carry Look Ahead (CLA) and Ripple Carry (R-C) adder have been studied, designed and compared in terms of area consumption and time requirement. The simulation results show that the CLA adder performs faster with optimized area consumption. Verilog Hardware Description Language (HDL) is used for designing the model with the help of Altera Quartus II Electronic Design Automation (EDA) tool. EDA synthesis tools make it easy to develop an HDL model and which can be synthesized into target-specific architectures. Whereas, the HDL based modeling provides shorter development phases with continuous testing and verification of the system performance and behavior. After successful functional and timing simulations of the CLA based BCD adder, the design has been downloaded to physical FPGA device. For FPGA implementation, the Altera DE2 board has been used which contains Altera Cyclone II 2C35 FPGA device. World Scientific and Engineering Academy and Society 2012 Article PeerReviewed application/pdf en http://irep.iium.edu.my/27422/1/Hardware_Modeling_of_Binary_Coded_Decimal_Adder_in_FPGA.pdf Ibrahimy, Muhammad Ibn and Ahsan, Md. Rezwanul and Bambang Soeroso, Iksannurazmi (2012) Hardware modeling of binary coded decimal adder in FPGA. WSEAS Transactions on Computers, 11 (10). pp. 366-375. ISSN 2224-2872 http://wseas.org/wseas/cms.action?id=2797
repository_type	Digital Repository
institution_category	Local University
institution	International Islamic University Malaysia
building	IIUM Repository
collection	Online Access
language	English
topic	T Technology (General)
spellingShingle	T Technology (General) Ibrahimy, Muhammad Ibn Ahsan, Md. Rezwanul Bambang Soeroso, Iksannurazmi Hardware modeling of binary coded decimal adder in FPGA
description	There are insignificant relevant research works available which are involved with the Field Programmable Gate Array (FPGA) based hardware implementation of Binary Coded Decimal (BCD) adder. This is because, the FPGA based hardware realization is quiet new and still developing field of research. The article illustrates the design and hardware modeling of a BCD adder. Among the types of adders, Carry Look Ahead (CLA) and Ripple Carry (R-C) adder have been studied, designed and compared in terms of area consumption and time requirement. The simulation results show that the CLA adder performs faster with optimized area consumption. Verilog Hardware Description Language (HDL) is used for designing the model with the help of Altera Quartus II Electronic Design Automation (EDA) tool. EDA synthesis tools make it easy to develop an HDL model and which can be synthesized into target-specific architectures. Whereas, the HDL based modeling provides shorter development phases with continuous testing and verification of the system performance and behavior. After successful functional and timing simulations of the CLA based BCD adder, the design has been downloaded to physical FPGA device. For FPGA implementation, the Altera DE2 board has been used which contains Altera Cyclone II 2C35 FPGA device.
format	Article
author	Ibrahimy, Muhammad Ibn Ahsan, Md. Rezwanul Bambang Soeroso, Iksannurazmi
author_facet	Ibrahimy, Muhammad Ibn Ahsan, Md. Rezwanul Bambang Soeroso, Iksannurazmi
author_sort	Ibrahimy, Muhammad Ibn
title	Hardware modeling of binary coded decimal adder in FPGA
title_short	Hardware modeling of binary coded decimal adder in FPGA
title_full	Hardware modeling of binary coded decimal adder in FPGA
title_fullStr	Hardware modeling of binary coded decimal adder in FPGA
title_full_unstemmed	Hardware modeling of binary coded decimal adder in FPGA
title_sort	hardware modeling of binary coded decimal adder in fpga
publisher	World Scientific and Engineering Academy and Society
publishDate	2012
url	http://irep.iium.edu.my/27422/ http://irep.iium.edu.my/27422/ http://irep.iium.edu.my/27422/1/Hardware_Modeling_of_Binary_Coded_Decimal_Adder_in_FPGA.pdf
first_indexed	2023-09-18T20:40:45Z
last_indexed	2023-09-18T20:40:45Z
_version_	1777409348357586944

Hardware modeling of binary coded decimal adder in FPGA

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