Design of a 5GHz phase-locked loop
Noise or jitter performance is a major concern in the design of phase-locked loop (PLL). Linearity and speed issues are of relevance when receiving data at gigahertz speed. The main function of a PLL circuit is to generate stable higher frequencies (GHz) output from a lower input frequency signal. P...
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2011
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| Online Access: | http://irep.iium.edu.my/15122/ http://irep.iium.edu.my/15122/ http://irep.iium.edu.my/15122/1/06088316.pdf |
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iium-151222012-05-06T10:04:00Z http://irep.iium.edu.my/15122/ Design of a 5GHz phase-locked loop Mohamad Ashari, Zainab Nordin, Anis Nurashikin Ibrahimy, Muhammad Ibn TK7885 Computer engineering Noise or jitter performance is a major concern in the design of phase-locked loop (PLL). Linearity and speed issues are of relevance when receiving data at gigahertz speed. The main function of a PLL circuit is to generate stable higher frequencies (GHz) output from a lower input frequency signal. PLLs are often used in communication technology to implement a variety of functions such as clock recovery, frequency multiplication, and clock synchronization. This paper presents the design and simulation results of PLL with low jitter performance. The key goal is to design and develop an analog PLL circuit for 5 GHz clock data recovery circuit. The PLL comprises of a phase frequency detector (PFD), low pass filter, voltage controlled oscillator (VCO), and feedback divider. In this work, analog mixed-signal architecture of PLL is simulated using hardware discipline modeling language, Verilog-AMS HDL. Multilingual and Mixed-Signal simulator SMASH software has been used for the Verilog-AMS design. A 5 GHz PLL with less jitter was successfully designed in this work. 2011-09 Conference or Workshop Item PeerReviewed application/pdf en http://irep.iium.edu.my/15122/1/06088316.pdf Mohamad Ashari, Zainab and Nordin, Anis Nurashikin and Ibrahimy, Muhammad Ibn (2011) Design of a 5GHz phase-locked loop. In: Micro and Nanoelectronics (RSM), 2011 IEEE Regional Symposium on, 28-30 Sept., 2011, Kota Kinabalu, Malaysia. http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6086117 |
| repository_type |
Digital Repository |
| institution_category |
Local University |
| institution |
International Islamic University Malaysia |
| building |
IIUM Repository |
| collection |
Online Access |
| language |
English |
| topic |
TK7885 Computer engineering |
| spellingShingle |
TK7885 Computer engineering Mohamad Ashari, Zainab Nordin, Anis Nurashikin Ibrahimy, Muhammad Ibn Design of a 5GHz phase-locked loop |
| description |
Noise or jitter performance is a major concern in the design of phase-locked loop (PLL). Linearity and speed issues are of relevance when receiving data at gigahertz speed. The main function of a PLL circuit is to generate stable higher frequencies (GHz) output from a lower input frequency signal. PLLs are often used in communication technology to implement a variety of functions such as clock recovery, frequency multiplication, and clock synchronization. This paper presents the design and simulation results of PLL with low jitter performance. The key goal is to design and develop an analog PLL circuit for 5 GHz clock data recovery circuit. The PLL comprises of a phase frequency detector (PFD), low pass filter, voltage controlled oscillator (VCO), and feedback divider. In this work, analog mixed-signal architecture of PLL is simulated using hardware discipline modeling language, Verilog-AMS HDL. Multilingual and Mixed-Signal simulator SMASH software has been used for the Verilog-AMS design. A 5 GHz PLL with less jitter was successfully designed in this work. |
| format |
Conference or Workshop Item |
| author |
Mohamad Ashari, Zainab Nordin, Anis Nurashikin Ibrahimy, Muhammad Ibn |
| author_facet |
Mohamad Ashari, Zainab Nordin, Anis Nurashikin Ibrahimy, Muhammad Ibn |
| author_sort |
Mohamad Ashari, Zainab |
| title |
Design of a 5GHz phase-locked loop |
| title_short |
Design of a 5GHz phase-locked loop |
| title_full |
Design of a 5GHz phase-locked loop |
| title_fullStr |
Design of a 5GHz phase-locked loop |
| title_full_unstemmed |
Design of a 5GHz phase-locked loop |
| title_sort |
design of a 5ghz phase-locked loop |
| publishDate |
2011 |
| url |
http://irep.iium.edu.my/15122/ http://irep.iium.edu.my/15122/ http://irep.iium.edu.my/15122/1/06088316.pdf |
| first_indexed |
2023-09-18T20:24:09Z |
| last_indexed |
2023-09-18T20:24:09Z |
| _version_ |
1777408304555753472 |