A low-complexity, hardware architecture for a parametric, real-time LSF speech decoder

One of the main objectives of the widely used MPEG4 audio standard was to provide a technical framework for audio coding suited for low bit rate wireless communication. All variants of the MPEG4 audio coders use a Linear Prediction (LP) filtering system. The LP filter coefficients are calc...

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Main Authors:	Mabrouk, Ahmed Hassan, Hassim, Norhidayah
Format:	Conference or Workshop Item
Language:	English
Published:	2011
Subjects:	QA75 Electronic computers. Computer science T Technology (General)
Online Access:	http://irep.iium.edu.my/15104/ http://irep.iium.edu.my/15104/ http://irep.iium.edu.my/15104/1/05973878_002.pdf

id	iium-15104
recordtype	eprints
spelling	iium-151042012-05-10T05:52:03Z http://irep.iium.edu.my/15104/ A low-complexity, hardware architecture for a parametric, real-time LSF speech decoder Mabrouk, Ahmed Hassan Hassim, Norhidayah QA75 Electronic computers. Computer science T Technology (General) One of the main objectives of the widely used MPEG4 audio standard was to provide a technical framework for audio coding suited for low bit rate wireless communication. All variants of the MPEG4 audio coders use a Linear Prediction (LP) filtering system. The LP filter coefficients are calculated based on the Line Spectral Frequencies (LSF) parameters due to their excellent quantization characteristics. This work presents a hardware architecture that implements the conversion of the LSF parameters into the LP coefficients and the LP synthesis filter. The LSF conversion module is based on a simplified algorithm that cuts down on many arithmetic operations and thus results in a low gate count module. The architecture was implemented on Xilinx Virtex5 FPGA platform for performance measurement and verification. Module speeds are reported in terms of the number of clock cycles taken by each of their sub-modules to show suitability for real-time applications. Synthesis results are reported using various degrees of parallelism to explore the trade-off between gate count and time delay. Fixed-point implementation was carried out in a way that kept the original precision of the LSF parameters and input data in order to mitigate the severe impact of the tight bit rate budget. 2011 Conference or Workshop Item NonPeerReviewed application/pdf en http://irep.iium.edu.my/15104/1/05973878_002.pdf Mabrouk, Ahmed Hassan and Hassim, Norhidayah (2011) A low-complexity, hardware architecture for a parametric, real-time LSF speech decoder. In: The 15th IEEE International Symposium on Consumer Electronics (ISCE 2011), 14-17 June 2011, Singapore. http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=05973878
repository_type	Digital Repository
institution_category	Local University
institution	International Islamic University Malaysia
building	IIUM Repository
collection	Online Access
language	English
topic	QA75 Electronic computers. Computer science T Technology (General)
spellingShingle	QA75 Electronic computers. Computer science T Technology (General) Mabrouk, Ahmed Hassan Hassim, Norhidayah A low-complexity, hardware architecture for a parametric, real-time LSF speech decoder
description	One of the main objectives of the widely used MPEG4 audio standard was to provide a technical framework for audio coding suited for low bit rate wireless communication. All variants of the MPEG4 audio coders use a Linear Prediction (LP) filtering system. The LP filter coefficients are calculated based on the Line Spectral Frequencies (LSF) parameters due to their excellent quantization characteristics. This work presents a hardware architecture that implements the conversion of the LSF parameters into the LP coefficients and the LP synthesis filter. The LSF conversion module is based on a simplified algorithm that cuts down on many arithmetic operations and thus results in a low gate count module. The architecture was implemented on Xilinx Virtex5 FPGA platform for performance measurement and verification. Module speeds are reported in terms of the number of clock cycles taken by each of their sub-modules to show suitability for real-time applications. Synthesis results are reported using various degrees of parallelism to explore the trade-off between gate count and time delay. Fixed-point implementation was carried out in a way that kept the original precision of the LSF parameters and input data in order to mitigate the severe impact of the tight bit rate budget.
format	Conference or Workshop Item
author	Mabrouk, Ahmed Hassan Hassim, Norhidayah
author_facet	Mabrouk, Ahmed Hassan Hassim, Norhidayah
author_sort	Mabrouk, Ahmed Hassan
title	A low-complexity, hardware architecture for a parametric, real-time LSF speech decoder
title_short	A low-complexity, hardware architecture for a parametric, real-time LSF speech decoder
title_full	A low-complexity, hardware architecture for a parametric, real-time LSF speech decoder
title_fullStr	A low-complexity, hardware architecture for a parametric, real-time LSF speech decoder
title_full_unstemmed	A low-complexity, hardware architecture for a parametric, real-time LSF speech decoder
title_sort	low-complexity, hardware architecture for a parametric, real-time lsf speech decoder
publishDate	2011
url	http://irep.iium.edu.my/15104/ http://irep.iium.edu.my/15104/ http://irep.iium.edu.my/15104/1/05973878_002.pdf
first_indexed	2023-09-18T20:24:08Z
last_indexed	2023-09-18T20:24:08Z
_version_	1777408303521857536

A low-complexity, hardware architecture for a parametric, real-time LSF speech decoder

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