Design of a current comparator for quaternary multi valued analog to digital converter

A low-power quaternary comparator circuit using current-mode CMOS multiple-valued logic (MVL) circuits has been presented in this paper. Existing MVL comparator circuits consume high power. The circuit presented in this paper has been shown low power digital output. It has been simulated with PSPICE...

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Main Authors: Farhana, Soheli, Alam, A. H. M. Zahirul, Khan, Sheroz, Rahman, Mohammed Ataur
Format: Conference or Workshop Item
Language:English
Published: 2011
Subjects:
Online Access:http://irep.iium.edu.my/11857/
http://irep.iium.edu.my/11857/
http://irep.iium.edu.my/11857/1/Design_of_a_current_comparator_for_quaternary_multi_valued_analog_to_digital_converter.pdf
id iium-11857
recordtype eprints
spelling iium-118572012-12-14T00:57:44Z http://irep.iium.edu.my/11857/ Design of a current comparator for quaternary multi valued analog to digital converter Farhana, Soheli Alam, A. H. M. Zahirul Khan, Sheroz Rahman, Mohammed Ataur TK Electrical engineering. Electronics Nuclear engineering A low-power quaternary comparator circuit using current-mode CMOS multiple-valued logic (MVL) circuits has been presented in this paper. Existing MVL comparator circuits consume high power. The circuit presented in this paper has been shown low power digital output. It has been simulated with PSPICE using the transistor model parameter values of the BSIM3 NMOS model V3.2 for 0.13 μm CMOS process. With a 1.3-volt power supply, simulations show that the proposed quaternary comparator consumes 0.107 mW total average static power and a sampling rate 500MHz. Power and speed for comparators designed in these technologies are discussed. The comparator design is suitable for the needs of mixed-signal integrated circuit design and can be implemented as a conversion circuit for systems based on multiple-valued logic design. 2011-12-01 Conference or Workshop Item PeerReviewed application/pdf en http://irep.iium.edu.my/11857/1/Design_of_a_current_comparator_for_quaternary_multi_valued_analog_to_digital_converter.pdf Farhana, Soheli and Alam, A. H. M. Zahirul and Khan, Sheroz and Rahman, Mohammed Ataur (2011) Design of a current comparator for quaternary multi valued analog to digital converter. In: 2011 IEEE Regional Symposium on Micro and Nanoelectronics (RSM), 28-30 September, Kota Kinabalu, Malaysia. http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6088321&tag=1
repository_type Digital Repository
institution_category Local University
institution International Islamic University Malaysia
building IIUM Repository
collection Online Access
language English
topic TK Electrical engineering. Electronics Nuclear engineering
spellingShingle TK Electrical engineering. Electronics Nuclear engineering
Farhana, Soheli
Alam, A. H. M. Zahirul
Khan, Sheroz
Rahman, Mohammed Ataur
Design of a current comparator for quaternary multi valued analog to digital converter
description A low-power quaternary comparator circuit using current-mode CMOS multiple-valued logic (MVL) circuits has been presented in this paper. Existing MVL comparator circuits consume high power. The circuit presented in this paper has been shown low power digital output. It has been simulated with PSPICE using the transistor model parameter values of the BSIM3 NMOS model V3.2 for 0.13 μm CMOS process. With a 1.3-volt power supply, simulations show that the proposed quaternary comparator consumes 0.107 mW total average static power and a sampling rate 500MHz. Power and speed for comparators designed in these technologies are discussed. The comparator design is suitable for the needs of mixed-signal integrated circuit design and can be implemented as a conversion circuit for systems based on multiple-valued logic design.
format Conference or Workshop Item
author Farhana, Soheli
Alam, A. H. M. Zahirul
Khan, Sheroz
Rahman, Mohammed Ataur
author_facet Farhana, Soheli
Alam, A. H. M. Zahirul
Khan, Sheroz
Rahman, Mohammed Ataur
author_sort Farhana, Soheli
title Design of a current comparator for quaternary multi valued analog to digital converter
title_short Design of a current comparator for quaternary multi valued analog to digital converter
title_full Design of a current comparator for quaternary multi valued analog to digital converter
title_fullStr Design of a current comparator for quaternary multi valued analog to digital converter
title_full_unstemmed Design of a current comparator for quaternary multi valued analog to digital converter
title_sort design of a current comparator for quaternary multi valued analog to digital converter
publishDate 2011
url http://irep.iium.edu.my/11857/
http://irep.iium.edu.my/11857/
http://irep.iium.edu.my/11857/1/Design_of_a_current_comparator_for_quaternary_multi_valued_analog_to_digital_converter.pdf
first_indexed 2023-09-18T20:21:07Z
last_indexed 2023-09-18T20:21:07Z
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