A Bayesian network-based framework with Constraint Satisfaction Problem (CSP)formulations for FPGA system design

A Bayesian network-based framework with Constraint Satisfaction Problem (CSP)formulations for FPGA system design

In recent years, there has been a growing interest in IP-reuse for SoCs in order to bridge the gap between the silicon capacity and the design productivity. This research work investigates how our proposed methodology can be used to partition and schedule a JPEG encoder IP core onto an FPGA. We wi...

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Main Authors: Azman, Amelia Wong, Bigdeli, Abbas, Mohd-Mustafah, Yasir, Biglari-Abhari, Morteza, Lovell, Brian
Format: Conference or Workshop Item
Language:English
Published: 2010
Subjects:
QA76 Computer software
Online Access:http://irep.iium.edu.my/102/
http://irep.iium.edu.my/102/
http://irep.iium.edu.my/102/1/ASAP.pdf
id iium-102
recordtype eprints
spelling iium-1022011-05-12T03:58:07Z http://irep.iium.edu.my/102/ A Bayesian network-based framework with Constraint Satisfaction Problem (CSP)formulations for FPGA system design Azman, Amelia Wong Bigdeli, Abbas Mohd-Mustafah, Yasir Biglari-Abhari, Morteza Lovell, Brian QA76 Computer software In recent years, there has been a growing interest in IP-reuse for SoCs in order to bridge the gap between the silicon capacity and the design productivity. This research work investigates how our proposed methodology can be used to partition and schedule a JPEG encoder IP core onto an FPGA. We will also describe a novel Constraint Satisfaction Problem (CSP) formulations that are used in the proposed framework. At the same time, we will also demonstrate the effectiveness of CSP in the Bayesian Network-based framework. 2010-07-07 Conference or Workshop Item PeerReviewed application/pdf en http://irep.iium.edu.my/102/1/ASAP.pdf Azman, Amelia Wong and Bigdeli, Abbas and Mohd-Mustafah, Yasir and Biglari-Abhari, Morteza and Lovell, Brian (2010) A Bayesian network-based framework with Constraint Satisfaction Problem (CSP)formulations for FPGA system design. In: 21st IEEE International Conference on Application-specific Systems Architectures and Processors (ASAP 2010), 7-9 July 2010, Rennes, France. http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5540784&isnumber=5540749
repository_type Digital Repository
institution_category Local University
institution International Islamic University Malaysia
building IIUM Repository
collection Online Access
language English
topic QA76 Computer software
spellingShingle QA76 Computer software
Azman, Amelia Wong
Bigdeli, Abbas
Mohd-Mustafah, Yasir
Biglari-Abhari, Morteza
Lovell, Brian
A Bayesian network-based framework with Constraint Satisfaction Problem (CSP)formulations for FPGA system design
description In recent years, there has been a growing interest in IP-reuse for SoCs in order to bridge the gap between the silicon capacity and the design productivity. This research work investigates how our proposed methodology can be used to partition and schedule a JPEG encoder IP core onto an FPGA. We will also describe a novel Constraint Satisfaction Problem (CSP) formulations that are used in the proposed framework. At the same time, we will also demonstrate the effectiveness of CSP in the Bayesian Network-based framework.
format Conference or Workshop Item
author Azman, Amelia Wong
Bigdeli, Abbas
Mohd-Mustafah, Yasir
Biglari-Abhari, Morteza
Lovell, Brian
author_facet Azman, Amelia Wong
Bigdeli, Abbas
Mohd-Mustafah, Yasir
Biglari-Abhari, Morteza
Lovell, Brian
author_sort Azman, Amelia Wong
title A Bayesian network-based framework with Constraint Satisfaction Problem (CSP)formulations for FPGA system design
title_short A Bayesian network-based framework with Constraint Satisfaction Problem (CSP)formulations for FPGA system design
title_full A Bayesian network-based framework with Constraint Satisfaction Problem (CSP)formulations for FPGA system design
title_fullStr A Bayesian network-based framework with Constraint Satisfaction Problem (CSP)formulations for FPGA system design
title_full_unstemmed A Bayesian network-based framework with Constraint Satisfaction Problem (CSP)formulations for FPGA system design
title_sort bayesian network-based framework with constraint satisfaction problem (csp)formulations for fpga system design
publishDate 2010
url http://irep.iium.edu.my/102/
http://irep.iium.edu.my/102/
http://irep.iium.edu.my/102/1/ASAP.pdf
first_indexed 2023-09-18T20:07:03Z
last_indexed 2023-09-18T20:07:03Z
_version_ 1777407228904472576

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